![Laurent Pinchart](/assets/img/avatar_default.png)
The WPF needs access to the current display list to configure writeback. Add a display list pointer to the VSP1 entity .configure_stream() operation. Only display pipelines can make use of the display list there as mem-to-mem pipelines don't have access to a display list at stream configuration time. This is not an issue as writeback is only used for display pipelines. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
286 lines
7.1 KiB
C
286 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* vsp1_clu.c -- R-Car VSP1 Cubic Look-Up Table
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*
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* Copyright (C) 2015-2016 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*/
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <media/v4l2-subdev.h>
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#include "vsp1.h"
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#include "vsp1_clu.h"
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#include "vsp1_dl.h"
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#define CLU_MIN_SIZE 4U
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#define CLU_MAX_SIZE 8190U
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#define CLU_SIZE (17 * 17 * 17)
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/* -----------------------------------------------------------------------------
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* Device Access
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*/
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static inline void vsp1_clu_write(struct vsp1_clu *clu,
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struct vsp1_dl_body *dlb, u32 reg, u32 data)
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{
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vsp1_dl_body_write(dlb, reg, data);
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}
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/* -----------------------------------------------------------------------------
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* Controls
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*/
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#define V4L2_CID_VSP1_CLU_TABLE (V4L2_CID_USER_BASE | 0x1001)
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#define V4L2_CID_VSP1_CLU_MODE (V4L2_CID_USER_BASE | 0x1002)
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#define V4L2_CID_VSP1_CLU_MODE_2D 0
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#define V4L2_CID_VSP1_CLU_MODE_3D 1
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static int clu_set_table(struct vsp1_clu *clu, struct v4l2_ctrl *ctrl)
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{
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struct vsp1_dl_body *dlb;
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unsigned int i;
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dlb = vsp1_dl_body_get(clu->pool);
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if (!dlb)
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return -ENOMEM;
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vsp1_dl_body_write(dlb, VI6_CLU_ADDR, 0);
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for (i = 0; i < CLU_SIZE; ++i)
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vsp1_dl_body_write(dlb, VI6_CLU_DATA, ctrl->p_new.p_u32[i]);
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spin_lock_irq(&clu->lock);
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swap(clu->clu, dlb);
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spin_unlock_irq(&clu->lock);
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vsp1_dl_body_put(dlb);
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return 0;
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}
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static int clu_s_ctrl(struct v4l2_ctrl *ctrl)
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{
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struct vsp1_clu *clu =
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container_of(ctrl->handler, struct vsp1_clu, ctrls);
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switch (ctrl->id) {
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case V4L2_CID_VSP1_CLU_TABLE:
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clu_set_table(clu, ctrl);
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break;
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case V4L2_CID_VSP1_CLU_MODE:
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clu->mode = ctrl->val;
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break;
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}
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return 0;
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}
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static const struct v4l2_ctrl_ops clu_ctrl_ops = {
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.s_ctrl = clu_s_ctrl,
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};
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static const struct v4l2_ctrl_config clu_table_control = {
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.ops = &clu_ctrl_ops,
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.id = V4L2_CID_VSP1_CLU_TABLE,
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.name = "Look-Up Table",
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.type = V4L2_CTRL_TYPE_U32,
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.min = 0x00000000,
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.max = 0x00ffffff,
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.step = 1,
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.def = 0,
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.dims = { 17, 17, 17 },
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};
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static const char * const clu_mode_menu[] = {
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"2D",
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"3D",
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NULL,
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};
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static const struct v4l2_ctrl_config clu_mode_control = {
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.ops = &clu_ctrl_ops,
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.id = V4L2_CID_VSP1_CLU_MODE,
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.name = "Mode",
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.type = V4L2_CTRL_TYPE_MENU,
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.min = 0,
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.max = 1,
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.def = 1,
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.qmenu = clu_mode_menu,
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};
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/* -----------------------------------------------------------------------------
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* V4L2 Subdevice Pad Operations
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*/
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static const unsigned int clu_codes[] = {
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MEDIA_BUS_FMT_ARGB8888_1X32,
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MEDIA_BUS_FMT_AHSV8888_1X32,
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MEDIA_BUS_FMT_AYUV8_1X32,
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};
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static int clu_enum_mbus_code(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_mbus_code_enum *code)
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{
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return vsp1_subdev_enum_mbus_code(subdev, cfg, code, clu_codes,
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ARRAY_SIZE(clu_codes));
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}
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static int clu_enum_frame_size(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_frame_size_enum *fse)
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{
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return vsp1_subdev_enum_frame_size(subdev, cfg, fse, CLU_MIN_SIZE,
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CLU_MIN_SIZE, CLU_MAX_SIZE,
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CLU_MAX_SIZE);
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}
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static int clu_set_format(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_format *fmt)
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{
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return vsp1_subdev_set_pad_format(subdev, cfg, fmt, clu_codes,
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ARRAY_SIZE(clu_codes),
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CLU_MIN_SIZE, CLU_MIN_SIZE,
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CLU_MAX_SIZE, CLU_MAX_SIZE);
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}
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/* -----------------------------------------------------------------------------
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* V4L2 Subdevice Operations
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*/
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static const struct v4l2_subdev_pad_ops clu_pad_ops = {
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.init_cfg = vsp1_entity_init_cfg,
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.enum_mbus_code = clu_enum_mbus_code,
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.enum_frame_size = clu_enum_frame_size,
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.get_fmt = vsp1_subdev_get_pad_format,
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.set_fmt = clu_set_format,
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};
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static const struct v4l2_subdev_ops clu_ops = {
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.pad = &clu_pad_ops,
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};
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/* -----------------------------------------------------------------------------
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* VSP1 Entity Operations
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*/
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static void clu_configure_stream(struct vsp1_entity *entity,
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struct vsp1_pipeline *pipe,
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struct vsp1_dl_list *dl,
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struct vsp1_dl_body *dlb)
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{
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struct vsp1_clu *clu = to_clu(&entity->subdev);
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struct v4l2_mbus_framefmt *format;
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/*
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* The yuv_mode can't be changed during streaming. Cache it internally
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* for future runtime configuration calls.
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*/
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format = vsp1_entity_get_pad_format(&clu->entity,
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clu->entity.config,
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CLU_PAD_SINK);
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clu->yuv_mode = format->code == MEDIA_BUS_FMT_AYUV8_1X32;
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}
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static void clu_configure_frame(struct vsp1_entity *entity,
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struct vsp1_pipeline *pipe,
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struct vsp1_dl_list *dl,
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struct vsp1_dl_body *dlb)
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{
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struct vsp1_clu *clu = to_clu(&entity->subdev);
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struct vsp1_dl_body *clu_dlb;
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unsigned long flags;
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u32 ctrl = VI6_CLU_CTRL_AAI | VI6_CLU_CTRL_MVS | VI6_CLU_CTRL_EN;
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/* 2D mode can only be used with the YCbCr pixel encoding. */
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if (clu->mode == V4L2_CID_VSP1_CLU_MODE_2D && clu->yuv_mode)
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ctrl |= VI6_CLU_CTRL_AX1I_2D | VI6_CLU_CTRL_AX2I_2D
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| VI6_CLU_CTRL_OS0_2D | VI6_CLU_CTRL_OS1_2D
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| VI6_CLU_CTRL_OS2_2D | VI6_CLU_CTRL_M2D;
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vsp1_clu_write(clu, dlb, VI6_CLU_CTRL, ctrl);
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spin_lock_irqsave(&clu->lock, flags);
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clu_dlb = clu->clu;
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clu->clu = NULL;
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spin_unlock_irqrestore(&clu->lock, flags);
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if (clu_dlb) {
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vsp1_dl_list_add_body(dl, clu_dlb);
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/* Release our local reference. */
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vsp1_dl_body_put(clu_dlb);
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}
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}
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static void clu_destroy(struct vsp1_entity *entity)
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{
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struct vsp1_clu *clu = to_clu(&entity->subdev);
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vsp1_dl_body_pool_destroy(clu->pool);
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}
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static const struct vsp1_entity_operations clu_entity_ops = {
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.configure_stream = clu_configure_stream,
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.configure_frame = clu_configure_frame,
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.destroy = clu_destroy,
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};
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/* -----------------------------------------------------------------------------
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* Initialization and Cleanup
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*/
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struct vsp1_clu *vsp1_clu_create(struct vsp1_device *vsp1)
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{
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struct vsp1_clu *clu;
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int ret;
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clu = devm_kzalloc(vsp1->dev, sizeof(*clu), GFP_KERNEL);
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if (clu == NULL)
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return ERR_PTR(-ENOMEM);
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spin_lock_init(&clu->lock);
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clu->entity.ops = &clu_entity_ops;
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clu->entity.type = VSP1_ENTITY_CLU;
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ret = vsp1_entity_init(vsp1, &clu->entity, "clu", 2, &clu_ops,
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MEDIA_ENT_F_PROC_VIDEO_LUT);
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if (ret < 0)
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return ERR_PTR(ret);
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/*
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* Pre-allocate a body pool, with 3 bodies allowing a userspace update
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* before the hardware has committed a previous set of tables, handling
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* both the queued and pending dl entries. One extra entry is added to
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* the CLU_SIZE to allow for the VI6_CLU_ADDR header.
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*/
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clu->pool = vsp1_dl_body_pool_create(clu->entity.vsp1, 3, CLU_SIZE + 1,
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0);
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if (!clu->pool)
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return ERR_PTR(-ENOMEM);
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/* Initialize the control handler. */
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v4l2_ctrl_handler_init(&clu->ctrls, 2);
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v4l2_ctrl_new_custom(&clu->ctrls, &clu_table_control, NULL);
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v4l2_ctrl_new_custom(&clu->ctrls, &clu_mode_control, NULL);
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clu->entity.subdev.ctrl_handler = &clu->ctrls;
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if (clu->ctrls.error) {
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dev_err(vsp1->dev, "clu: failed to initialize controls\n");
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ret = clu->ctrls.error;
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vsp1_entity_destroy(&clu->entity);
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return ERR_PTR(ret);
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}
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v4l2_ctrl_handler_setup(&clu->ctrls);
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return clu;
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}
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