![Kieran Bingham](/assets/img/avatar_default.png)
Calculate the top and bottom fields for the interlaced frames and utilise the extended display list command feature to implement the auto-field operations. This allows the DU to update the VSP2 registers dynamically based upon the currently processing field. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
176 lines
5.2 KiB
C
176 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* vsp1_pipe.h -- R-Car VSP1 Pipeline
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*
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*/
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#ifndef __VSP1_PIPE_H__
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#define __VSP1_PIPE_H__
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#include <linux/kref.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/wait.h>
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#include <media/media-entity.h>
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struct vsp1_dl_list;
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struct vsp1_rwpf;
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/*
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* struct vsp1_format_info - VSP1 video format description
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* @fourcc: V4L2 pixel format FCC identifier
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* @mbus: media bus format code
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* @hwfmt: VSP1 hardware format
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* @swap: swap register control
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* @planes: number of planes
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* @bpp: bits per pixel
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* @swap_yc: the Y and C components are swapped (Y comes before C)
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* @swap_uv: the U and V components are swapped (V comes before U)
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* @hsub: horizontal subsampling factor
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* @vsub: vertical subsampling factor
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* @alpha: has an alpha channel
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*/
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struct vsp1_format_info {
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u32 fourcc;
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unsigned int mbus;
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unsigned int hwfmt;
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unsigned int swap;
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unsigned int planes;
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unsigned int bpp[3];
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bool swap_yc;
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bool swap_uv;
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unsigned int hsub;
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unsigned int vsub;
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bool alpha;
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};
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enum vsp1_pipeline_state {
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VSP1_PIPELINE_STOPPED,
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VSP1_PIPELINE_RUNNING,
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VSP1_PIPELINE_STOPPING,
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};
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/*
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* struct vsp1_partition_window - Partition window coordinates
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* @left: horizontal coordinate of the partition start in pixels relative to the
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* left edge of the image
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* @width: partition width in pixels
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*/
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struct vsp1_partition_window {
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unsigned int left;
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unsigned int width;
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};
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/*
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* struct vsp1_partition - A description of a slice for the partition algorithm
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* @rpf: The RPF partition window configuration
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* @uds_sink: The UDS input partition window configuration
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* @uds_source: The UDS output partition window configuration
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* @sru: The SRU partition window configuration
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* @wpf: The WPF partition window configuration
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*/
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struct vsp1_partition {
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struct vsp1_partition_window rpf;
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struct vsp1_partition_window uds_sink;
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struct vsp1_partition_window uds_source;
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struct vsp1_partition_window sru;
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struct vsp1_partition_window wpf;
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};
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/*
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* struct vsp1_pipeline - A VSP1 hardware pipeline
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* @pipe: the media pipeline
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* @irqlock: protects the pipeline state
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* @state: current state
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* @wq: wait queue to wait for state change completion
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* @frame_end: frame end interrupt handler
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* @lock: protects the pipeline use count and stream count
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* @kref: pipeline reference count
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* @stream_count: number of streaming video nodes
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* @buffers_ready: bitmask of RPFs and WPFs with at least one buffer available
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* @sequence: frame sequence number
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* @num_inputs: number of RPFs
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* @inputs: array of RPFs in the pipeline (indexed by RPF index)
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* @output: WPF at the output of the pipeline
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* @brx: BRx entity, if present
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* @hgo: HGO entity, if present
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* @hgt: HGT entity, if present
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* @lif: LIF entity, if present
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* @uds: UDS entity, if present
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* @uds_input: entity at the input of the UDS, if the UDS is present
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* @entities: list of entities in the pipeline
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* @stream_config: cached stream configuration for video pipelines
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* @configured: when false the @stream_config shall be written to the hardware
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* @interlaced: True when the pipeline is configured in interlaced mode
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* @partitions: The number of partitions used to process one frame
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* @partition: The current partition for configuration to process
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* @part_table: The pre-calculated partitions used by the pipeline
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*/
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struct vsp1_pipeline {
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struct media_pipeline pipe;
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spinlock_t irqlock;
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enum vsp1_pipeline_state state;
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wait_queue_head_t wq;
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void (*frame_end)(struct vsp1_pipeline *pipe, unsigned int completion);
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struct mutex lock;
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struct kref kref;
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unsigned int stream_count;
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unsigned int buffers_ready;
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unsigned int sequence;
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unsigned int num_inputs;
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struct vsp1_rwpf *inputs[VSP1_MAX_RPF];
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struct vsp1_rwpf *output;
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struct vsp1_entity *brx;
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struct vsp1_entity *hgo;
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struct vsp1_entity *hgt;
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struct vsp1_entity *lif;
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struct vsp1_entity *uds;
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struct vsp1_entity *uds_input;
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/*
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* The order of this list must be identical to the order of the entities
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* in the pipeline, as it is assumed by the partition algorithm that we
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* can walk this list in sequence.
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*/
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struct list_head entities;
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struct vsp1_dl_body *stream_config;
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bool configured;
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bool interlaced;
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unsigned int partitions;
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struct vsp1_partition *partition;
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struct vsp1_partition *part_table;
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};
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void vsp1_pipeline_reset(struct vsp1_pipeline *pipe);
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void vsp1_pipeline_init(struct vsp1_pipeline *pipe);
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void vsp1_pipeline_run(struct vsp1_pipeline *pipe);
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bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe);
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int vsp1_pipeline_stop(struct vsp1_pipeline *pipe);
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bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe);
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void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe);
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void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
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struct vsp1_dl_body *dlb,
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unsigned int alpha);
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void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe,
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struct vsp1_partition *partition,
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unsigned int index,
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struct vsp1_partition_window *window);
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const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1,
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u32 fourcc);
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#endif /* __VSP1_PIPE_H__ */
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