549f3ae1be
This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx SoCs. SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works in ahci mode. Because of this, these nodes are marked "disabled" by default. In order to use pcie controller on evaluation boards do necessary modifications on board and enable (By replacing "disabled" with "okay") pcie and miphy from respective 'evb' dtsi file. Phy specific initialization was previously done from spear1340.c, which isn't required anymore as we have separate drivers for it. Remove it. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Mohit Kumar <mohit.kumar@st.com> [viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
317 lines
7.6 KiB
Plaintext
317 lines
7.6 KiB
Plaintext
/*
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* DTS file for all SPEAr1310 SoCs
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*
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* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "spear13xx.dtsi"
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/ {
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compatible = "st,spear1310";
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ahb {
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spics: spics@e0700000{
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compatible = "st,spear-spics-gpio";
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reg = <0xe0700000 0x1000>;
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st-spics,peripcfg-reg = <0x3b0>;
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st-spics,sw-enable-bit = <12>;
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st-spics,cs-value-bit = <11>;
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st-spics,cs-enable-mask = <3>;
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st-spics,cs-enable-shift = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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miphy0: miphy@eb800000 {
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compatible = "st,spear1310-miphy";
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reg = <0xeb800000 0x4000>;
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misc = <&misc>;
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phy-id = <0>;
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#phy-cells = <1>;
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status = "disabled";
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};
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miphy1: miphy@eb804000 {
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compatible = "st,spear1310-miphy";
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reg = <0xeb804000 0x4000>;
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misc = <&misc>;
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phy-id = <1>;
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#phy-cells = <1>;
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status = "disabled";
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};
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miphy2: miphy@eb808000 {
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compatible = "st,spear1310-miphy";
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reg = <0xeb808000 0x4000>;
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misc = <&misc>;
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phy-id = <2>;
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#phy-cells = <1>;
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status = "disabled";
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};
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ahci0: ahci@b1000000 {
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compatible = "snps,spear-ahci";
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reg = <0xb1000000 0x10000>;
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interrupts = <0 68 0x4>;
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phys = <&miphy0 0>;
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phy-names = "sata-phy";
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status = "disabled";
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};
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ahci1: ahci@b1800000 {
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compatible = "snps,spear-ahci";
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reg = <0xb1800000 0x10000>;
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interrupts = <0 69 0x4>;
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phys = <&miphy1 0>;
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phy-names = "sata-phy";
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status = "disabled";
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};
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ahci2: ahci@b4000000 {
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compatible = "snps,spear-ahci";
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reg = <0xb4000000 0x10000>;
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interrupts = <0 70 0x4>;
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phys = <&miphy2 0>;
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phy-names = "sata-phy";
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status = "disabled";
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};
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pcie0: pcie@b1000000 {
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compatible = "st,spear1340-pcie", "snps,dw-pcie";
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reg = <0xb1000000 0x4000>;
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interrupts = <0 68 0x4>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 0 68 0x4>;
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num-lanes = <1>;
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phys = <&miphy0 1>;
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phy-names = "pcie-phy";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
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0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
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status = "disabled";
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};
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pcie1: pcie@b1800000 {
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compatible = "st,spear1340-pcie", "snps,dw-pcie";
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reg = <0xb1800000 0x4000>;
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interrupts = <0 69 0x4>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 0 69 0x4>;
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num-lanes = <1>;
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phys = <&miphy1 1>;
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phy-names = "pcie-phy";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */
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0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
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status = "disabled";
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};
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pcie2: pcie@b4000000 {
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compatible = "st,spear1340-pcie", "snps,dw-pcie";
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reg = <0xb4000000 0x4000>;
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interrupts = <0 70 0x4>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 0 70 0x4>;
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num-lanes = <1>;
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phys = <&miphy2 1>;
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phy-names = "pcie-phy";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */
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0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
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status = "disabled";
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};
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gmac1: eth@5c400000 {
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compatible = "st,spear600-gmac";
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reg = <0x5c400000 0x8000>;
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interrupts = <0 95 0x4>;
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interrupt-names = "macirq";
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phy-mode = "mii";
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status = "disabled";
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};
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gmac2: eth@5c500000 {
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compatible = "st,spear600-gmac";
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reg = <0x5c500000 0x8000>;
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interrupts = <0 96 0x4>;
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interrupt-names = "macirq";
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phy-mode = "mii";
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status = "disabled";
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};
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gmac3: eth@5c600000 {
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compatible = "st,spear600-gmac";
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reg = <0x5c600000 0x8000>;
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interrupts = <0 97 0x4>;
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interrupt-names = "macirq";
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phy-mode = "rmii";
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status = "disabled";
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};
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gmac4: eth@5c700000 {
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compatible = "st,spear600-gmac";
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reg = <0x5c700000 0x8000>;
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interrupts = <0 98 0x4>;
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interrupt-names = "macirq";
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phy-mode = "rgmii";
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status = "disabled";
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};
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pinmux: pinmux@e0700000 {
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compatible = "st,spear1310-pinmux";
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reg = <0xe0700000 0x1000>;
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#gpio-range-cells = <3>;
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};
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apb {
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i2c1: i2c@5cd00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0x5cd00000 0x1000>;
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interrupts = <0 87 0x4>;
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status = "disabled";
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};
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i2c2: i2c@5ce00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0x5ce00000 0x1000>;
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interrupts = <0 88 0x4>;
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status = "disabled";
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};
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i2c3: i2c@5cf00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0x5cf00000 0x1000>;
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interrupts = <0 89 0x4>;
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status = "disabled";
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};
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i2c4: i2c@5d000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0x5d000000 0x1000>;
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interrupts = <0 90 0x4>;
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status = "disabled";
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};
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i2c5: i2c@5d100000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0x5d100000 0x1000>;
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interrupts = <0 91 0x4>;
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status = "disabled";
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};
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i2c6: i2c@5d200000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0x5d200000 0x1000>;
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interrupts = <0 92 0x4>;
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status = "disabled";
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};
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i2c7: i2c@5d300000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0x5d300000 0x1000>;
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interrupts = <0 93 0x4>;
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status = "disabled";
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};
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spi1: spi@5d400000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x5d400000 0x1000>;
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interrupts = <0 99 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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serial@5c800000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x5c800000 0x1000>;
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interrupts = <0 82 0x4>;
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status = "disabled";
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};
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serial@5c900000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x5c900000 0x1000>;
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interrupts = <0 83 0x4>;
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status = "disabled";
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};
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serial@5ca00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x5ca00000 0x1000>;
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interrupts = <0 84 0x4>;
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status = "disabled";
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};
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serial@5cb00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x5cb00000 0x1000>;
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interrupts = <0 85 0x4>;
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status = "disabled";
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};
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serial@5cc00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x5cc00000 0x1000>;
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interrupts = <0 86 0x4>;
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status = "disabled";
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};
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thermal@e07008c4 {
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st,thermal-flags = <0x7000>;
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};
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gpiopinctrl: gpio@d8400000 {
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compatible = "st,spear-plgpio";
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reg = <0xd8400000 0x1000>;
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interrupts = <0 100 0x4>;
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#interrupt-cells = <1>;
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interrupt-controller;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinmux 0 0 246>;
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status = "disabled";
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st-plgpio,ngpio = <246>;
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st-plgpio,enb-reg = <0xd0>;
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st-plgpio,wdata-reg = <0x90>;
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st-plgpio,dir-reg = <0xb0>;
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st-plgpio,ie-reg = <0x30>;
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st-plgpio,rdata-reg = <0x70>;
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st-plgpio,mis-reg = <0x10>;
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st-plgpio,eit-reg = <0x50>;
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};
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};
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};
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};
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