549f3ae1be
This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx SoCs. SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works in ahci mode. Because of this, these nodes are marked "disabled" by default. In order to use pcie controller on evaluation boards do necessary modifications on board and enable (By replacing "disabled" with "okay") pcie and miphy from respective 'evb' dtsi file. Phy specific initialization was previously done from spear1340.c, which isn't required anymore as we have separate drivers for it. Remove it. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Mohit Kumar <mohit.kumar@st.com> [viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
175 lines
4 KiB
Plaintext
175 lines
4 KiB
Plaintext
/*
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* DTS file for all SPEAr1340 SoCs
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*
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* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "spear13xx.dtsi"
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/ {
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compatible = "st,spear1340";
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ahb {
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spics: spics@e0700000{
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compatible = "st,spear-spics-gpio";
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reg = <0xe0700000 0x1000>;
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st-spics,peripcfg-reg = <0x42c>;
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st-spics,sw-enable-bit = <21>;
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st-spics,cs-value-bit = <20>;
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st-spics,cs-enable-mask = <3>;
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st-spics,cs-enable-shift = <18>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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miphy0: miphy@eb800000 {
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compatible = "st,spear1340-miphy";
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reg = <0xeb800000 0x4000>;
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misc = <&misc>;
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#phy-cells = <1>;
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status = "disabled";
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};
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ahci0: ahci@b1000000 {
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compatible = "snps,spear-ahci";
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reg = <0xb1000000 0x10000>;
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interrupts = <0 72 0x4>;
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phys = <&miphy0 0>;
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phy-names = "sata-phy";
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status = "disabled";
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};
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pcie0: pcie@b1000000 {
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compatible = "st,spear1340-pcie", "snps,dw-pcie";
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reg = <0xb1000000 0x4000>;
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interrupts = <0 68 0x4>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 0 68 0x4>;
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num-lanes = <1>;
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phys = <&miphy0 1>;
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phy-names = "pcie-phy";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
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0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
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status = "disabled";
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};
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i2s-play@b2400000 {
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compatible = "snps,designware-i2s";
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reg = <0xb2400000 0x10000>;
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interrupt-names = "play_irq";
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interrupts = <0 98 0x4
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0 99 0x4>;
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play;
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channel = <8>;
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status = "disabled";
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};
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i2s-rec@b2000000 {
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compatible = "snps,designware-i2s";
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reg = <0xb2000000 0x10000>;
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interrupt-names = "record_irq";
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interrupts = <0 100 0x4
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0 101 0x4>;
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record;
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channel = <8>;
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status = "disabled";
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};
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pinmux: pinmux@e0700000 {
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compatible = "st,spear1340-pinmux";
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reg = <0xe0700000 0x1000>;
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#gpio-range-cells = <3>;
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};
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pwm: pwm@e0180000 {
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compatible ="st,spear13xx-pwm";
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reg = <0xe0180000 0x1000>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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spdif-in@d0100000 {
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compatible = "st,spdif-in";
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reg = < 0xd0100000 0x20000
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0xd0110000 0x10000 >;
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interrupts = <0 84 0x4>;
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status = "disabled";
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};
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spdif-out@d0000000 {
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compatible = "st,spdif-out";
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reg = <0xd0000000 0x20000>;
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interrupts = <0 85 0x4>;
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status = "disabled";
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};
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spi1: spi@5d400000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x5d400000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 99 0x4>;
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status = "disabled";
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};
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apb {
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i2c1: i2c@b4000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xb4000000 0x1000>;
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interrupts = <0 104 0x4>;
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write-16bit;
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status = "disabled";
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};
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serial@b4100000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb4100000 0x1000>;
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interrupts = <0 105 0x4>;
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status = "disabled";
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dmas = <&dwdma0 0x600 0 0 1>, /* 0xC << 11 */
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<&dwdma0 0x680 0 1 0>; /* 0xD << 7 */
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dma-names = "tx", "rx";
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};
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thermal@e07008c4 {
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st,thermal-flags = <0x2a00>;
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};
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gpiopinctrl: gpio@e2800000 {
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compatible = "st,spear-plgpio";
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reg = <0xe2800000 0x1000>;
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interrupts = <0 107 0x4>;
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#interrupt-cells = <1>;
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interrupt-controller;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinmux 0 0 252>;
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status = "disabled";
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st-plgpio,ngpio = <250>;
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st-plgpio,wdata-reg = <0x40>;
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st-plgpio,dir-reg = <0x00>;
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st-plgpio,ie-reg = <0x80>;
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st-plgpio,rdata-reg = <0x20>;
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st-plgpio,mis-reg = <0xa0>;
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st-plgpio,eit-reg = <0x60>;
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};
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};
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};
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};
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