![Pawel Moll](/assets/img/avatar_default.png)
Components of the Versatile Express platform (configuration microcontrollers on motherboard and daughterboards in particular) talk to each other over a custom configuration bus. They provide miscellaneous functions (from clock generator control to energy sensors) which are represented as platform devices (and Device Tree nodes). The transactions on the bus can be generated by different "bridges" in the system, some of which are universal for the whole platform (for the price of high transfer latencies), others restricted to a subsystem (but much faster). Until now drivers for such functions were using custom "func" API, which is being replaced in this patch by regmap calls. This required: * a rework (and move to drivers/bus directory, as suggested by Samuel and Arnd) of the config bus core, which is much simpler now and uses device model infrastructure (class) to keep track of the bridges; non-DT case (soon to be retired anyway) is simply covered by a special device registration function * the new config-bus driver also takes over device population, so there is no need for special matching table for of_platform_populate nor "simple-bus" hack in the arm64 model dtsi file (relevant bindings documentation has been updated); this allows all the vexpress devices fit into normal device model, making it possible to remove plenty of early inits and other hacks in the near future * adaptation of the syscfg bridge implementation in the sysreg driver, again making it much simpler; there is a special case of the "energy" function spanning two registers, where they should be both defined in the tree now, but backward compatibility is maintained in the code * modification of the relevant drivers: * hwmon - just a straight-forward API change * power/reset driver - API change * regulator - API change plus error handling simplification * osc clock driver - this one required larger rework in order to turn in into a standard platform driver Signed-off-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Mark Brown <broonie@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Mike Turquette <mturquette@linaro.org>
399 lines
8.8 KiB
Plaintext
399 lines
8.8 KiB
Plaintext
/*
|
|
* ARM Ltd. Versatile Express
|
|
*
|
|
* CoreTile Express A15x2 A7x3
|
|
* Cortex-A15_A7 MPCore (V2P-CA15_A7)
|
|
*
|
|
* HBI-0249A
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
model = "V2P-CA15_CA7";
|
|
arm,hbi = <0x249>;
|
|
arm,vexpress,site = <0xf>;
|
|
compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
chosen { };
|
|
|
|
aliases {
|
|
serial0 = &v2m_serial0;
|
|
serial1 = &v2m_serial1;
|
|
serial2 = &v2m_serial2;
|
|
serial3 = &v2m_serial3;
|
|
i2c0 = &v2m_i2c_dvi;
|
|
i2c1 = &v2m_i2c_pcie;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0>;
|
|
cci-control-port = <&cci_control1>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <1>;
|
|
cci-control-port = <&cci_control1>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x100>;
|
|
cci-control-port = <&cci_control2>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x101>;
|
|
cci-control-port = <&cci_control2>;
|
|
};
|
|
|
|
cpu4: cpu@4 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x102>;
|
|
cci-control-port = <&cci_control2>;
|
|
};
|
|
};
|
|
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0 0x80000000 0 0x40000000>;
|
|
};
|
|
|
|
wdt@2a490000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0 0x2a490000 0 0x1000>;
|
|
interrupts = <0 98 4>;
|
|
clocks = <&oscclk6a>, <&oscclk6a>;
|
|
clock-names = "wdogclk", "apb_pclk";
|
|
};
|
|
|
|
hdlcd@2b000000 {
|
|
compatible = "arm,hdlcd";
|
|
reg = <0 0x2b000000 0 0x1000>;
|
|
interrupts = <0 85 4>;
|
|
clocks = <&oscclk5>;
|
|
clock-names = "pxlclk";
|
|
};
|
|
|
|
memory-controller@2b0a0000 {
|
|
compatible = "arm,pl341", "arm,primecell";
|
|
reg = <0 0x2b0a0000 0 0x1000>;
|
|
clocks = <&oscclk6a>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gic: interrupt-controller@2c001000 {
|
|
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0 0x2c001000 0 0x1000>,
|
|
<0 0x2c002000 0 0x1000>,
|
|
<0 0x2c004000 0 0x2000>,
|
|
<0 0x2c006000 0 0x2000>;
|
|
interrupts = <1 9 0xf04>;
|
|
};
|
|
|
|
cci@2c090000 {
|
|
compatible = "arm,cci-400";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0 0x2c090000 0 0x1000>;
|
|
ranges = <0x0 0x0 0x2c090000 0x10000>;
|
|
|
|
cci_control1: slave-if@4000 {
|
|
compatible = "arm,cci-400-ctrl-if";
|
|
interface-type = "ace";
|
|
reg = <0x4000 0x1000>;
|
|
};
|
|
|
|
cci_control2: slave-if@5000 {
|
|
compatible = "arm,cci-400-ctrl-if";
|
|
interface-type = "ace";
|
|
reg = <0x5000 0x1000>;
|
|
};
|
|
};
|
|
|
|
memory-controller@7ffd0000 {
|
|
compatible = "arm,pl354", "arm,primecell";
|
|
reg = <0 0x7ffd0000 0 0x1000>;
|
|
interrupts = <0 86 4>,
|
|
<0 87 4>;
|
|
clocks = <&oscclk6a>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
dma@7ff00000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0 0x7ff00000 0 0x1000>;
|
|
interrupts = <0 92 4>,
|
|
<0 88 4>,
|
|
<0 89 4>,
|
|
<0 90 4>,
|
|
<0 91 4>;
|
|
clocks = <&oscclk6a>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
scc@7fff0000 {
|
|
compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
|
|
reg = <0 0x7fff0000 0 0x1000>;
|
|
interrupts = <0 95 4>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <1 13 0xf08>,
|
|
<1 14 0xf08>,
|
|
<1 11 0xf08>,
|
|
<1 10 0xf08>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a15-pmu";
|
|
interrupts = <0 68 4>,
|
|
<0 69 4>;
|
|
};
|
|
|
|
oscclk6a: oscclk6a {
|
|
/* Reference 24MHz clock */
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "oscclk6a";
|
|
};
|
|
|
|
dcc {
|
|
compatible = "arm,vexpress,config-bus";
|
|
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
|
|
|
osc@0 {
|
|
/* A15 PLL 0 reference clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 0>;
|
|
freq-range = <17000000 50000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "oscclk0";
|
|
};
|
|
|
|
osc@1 {
|
|
/* A15 PLL 1 reference clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 1>;
|
|
freq-range = <17000000 50000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "oscclk1";
|
|
};
|
|
|
|
osc@2 {
|
|
/* A7 PLL 0 reference clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 2>;
|
|
freq-range = <17000000 50000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "oscclk2";
|
|
};
|
|
|
|
osc@3 {
|
|
/* A7 PLL 1 reference clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 3>;
|
|
freq-range = <17000000 50000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "oscclk3";
|
|
};
|
|
|
|
osc@4 {
|
|
/* External AXI master clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 4>;
|
|
freq-range = <20000000 40000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "oscclk4";
|
|
};
|
|
|
|
oscclk5: osc@5 {
|
|
/* HDLCD PLL reference clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 5>;
|
|
freq-range = <23750000 165000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "oscclk5";
|
|
};
|
|
|
|
smbclk: osc@6 {
|
|
/* Static memory controller clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 6>;
|
|
freq-range = <20000000 40000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "oscclk6";
|
|
};
|
|
|
|
osc@7 {
|
|
/* SYS PLL reference clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 7>;
|
|
freq-range = <17000000 50000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "oscclk7";
|
|
};
|
|
|
|
osc@8 {
|
|
/* DDR2 PLL reference clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 8>;
|
|
freq-range = <20000000 50000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "oscclk8";
|
|
};
|
|
|
|
volt@0 {
|
|
/* A15 CPU core voltage */
|
|
compatible = "arm,vexpress-volt";
|
|
arm,vexpress-sysreg,func = <2 0>;
|
|
regulator-name = "A15 Vcore";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
regulator-always-on;
|
|
label = "A15 Vcore";
|
|
};
|
|
|
|
volt@1 {
|
|
/* A7 CPU core voltage */
|
|
compatible = "arm,vexpress-volt";
|
|
arm,vexpress-sysreg,func = <2 1>;
|
|
regulator-name = "A7 Vcore";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
regulator-always-on;
|
|
label = "A7 Vcore";
|
|
};
|
|
|
|
amp@0 {
|
|
/* Total current for the two A15 cores */
|
|
compatible = "arm,vexpress-amp";
|
|
arm,vexpress-sysreg,func = <3 0>;
|
|
label = "A15 Icore";
|
|
};
|
|
|
|
amp@1 {
|
|
/* Total current for the three A7 cores */
|
|
compatible = "arm,vexpress-amp";
|
|
arm,vexpress-sysreg,func = <3 1>;
|
|
label = "A7 Icore";
|
|
};
|
|
|
|
temp@0 {
|
|
/* DCC internal temperature */
|
|
compatible = "arm,vexpress-temp";
|
|
arm,vexpress-sysreg,func = <4 0>;
|
|
label = "DCC";
|
|
};
|
|
|
|
power@0 {
|
|
/* Total power for the two A15 cores */
|
|
compatible = "arm,vexpress-power";
|
|
arm,vexpress-sysreg,func = <12 0>;
|
|
label = "A15 Pcore";
|
|
};
|
|
|
|
power@1 {
|
|
/* Total power for the three A7 cores */
|
|
compatible = "arm,vexpress-power";
|
|
arm,vexpress-sysreg,func = <12 1>;
|
|
label = "A7 Pcore";
|
|
};
|
|
|
|
energy@0 {
|
|
/* Total energy for the two A15 cores */
|
|
compatible = "arm,vexpress-energy";
|
|
arm,vexpress-sysreg,func = <13 0>, <13 1>;
|
|
label = "A15 Jcore";
|
|
};
|
|
|
|
energy@2 {
|
|
/* Total energy for the three A7 cores */
|
|
compatible = "arm,vexpress-energy";
|
|
arm,vexpress-sysreg,func = <13 2>, <13 3>;
|
|
label = "A7 Jcore";
|
|
};
|
|
};
|
|
|
|
smb {
|
|
compatible = "simple-bus";
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0x08000000 0x04000000>,
|
|
<1 0 0 0x14000000 0x04000000>,
|
|
<2 0 0 0x18000000 0x04000000>,
|
|
<3 0 0 0x1c000000 0x04000000>,
|
|
<4 0 0 0x0c000000 0x04000000>,
|
|
<5 0 0 0x10000000 0x04000000>;
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 63>;
|
|
interrupt-map = <0 0 0 &gic 0 0 4>,
|
|
<0 0 1 &gic 0 1 4>,
|
|
<0 0 2 &gic 0 2 4>,
|
|
<0 0 3 &gic 0 3 4>,
|
|
<0 0 4 &gic 0 4 4>,
|
|
<0 0 5 &gic 0 5 4>,
|
|
<0 0 6 &gic 0 6 4>,
|
|
<0 0 7 &gic 0 7 4>,
|
|
<0 0 8 &gic 0 8 4>,
|
|
<0 0 9 &gic 0 9 4>,
|
|
<0 0 10 &gic 0 10 4>,
|
|
<0 0 11 &gic 0 11 4>,
|
|
<0 0 12 &gic 0 12 4>,
|
|
<0 0 13 &gic 0 13 4>,
|
|
<0 0 14 &gic 0 14 4>,
|
|
<0 0 15 &gic 0 15 4>,
|
|
<0 0 16 &gic 0 16 4>,
|
|
<0 0 17 &gic 0 17 4>,
|
|
<0 0 18 &gic 0 18 4>,
|
|
<0 0 19 &gic 0 19 4>,
|
|
<0 0 20 &gic 0 20 4>,
|
|
<0 0 21 &gic 0 21 4>,
|
|
<0 0 22 &gic 0 22 4>,
|
|
<0 0 23 &gic 0 23 4>,
|
|
<0 0 24 &gic 0 24 4>,
|
|
<0 0 25 &gic 0 25 4>,
|
|
<0 0 26 &gic 0 26 4>,
|
|
<0 0 27 &gic 0 27 4>,
|
|
<0 0 28 &gic 0 28 4>,
|
|
<0 0 29 &gic 0 29 4>,
|
|
<0 0 30 &gic 0 30 4>,
|
|
<0 0 31 &gic 0 31 4>,
|
|
<0 0 32 &gic 0 32 4>,
|
|
<0 0 33 &gic 0 33 4>,
|
|
<0 0 34 &gic 0 34 4>,
|
|
<0 0 35 &gic 0 35 4>,
|
|
<0 0 36 &gic 0 36 4>,
|
|
<0 0 37 &gic 0 37 4>,
|
|
<0 0 38 &gic 0 38 4>,
|
|
<0 0 39 &gic 0 39 4>,
|
|
<0 0 40 &gic 0 40 4>,
|
|
<0 0 41 &gic 0 41 4>,
|
|
<0 0 42 &gic 0 42 4>;
|
|
|
|
/include/ "vexpress-v2m-rs1.dtsi"
|
|
};
|
|
};
|