![Adit Ranadive](/assets/img/avatar_default.png)
This patch series adds a driver for a paravirtual RDMA device. The device is developed for VMware's Virtual Machines and allows existing RDMA applications to continue to use existing Verbs API when deployed in VMs on ESXi. We recently did a presentation in the OFA Workshop [1] regarding this device. Description and RDMA Support ============================ The virtual device is exposed as a dual function PCIe device. One part is a virtual network device (VMXNet3) which provides networking properties like MAC, IP addresses to the RDMA part of the device. The networking properties are used to register GIDs required by RDMA applications to communicate. These patches add support and the all required infrastructure for letting applications use such a device. We support the mandatory Verbs API as well as the base memory management extensions (Local Inv, Send with Inv and Fast Register Work Requests). We currently support both Reliable Connected and Unreliable Datagram QPs but do not support Shared Receive Queues (SRQs). Also, we support the following types of Work Requests: o Send/Receive (with or without Immediate Data) o RDMA Write (with or without Immediate Data) o RDMA Read o Local Invalidate o Send with Invalidate o Fast Register Work Requests This version only adds support for version 1 of RoCE. We will add RoCEv2 support in a future patch. We do support registration of both MAC-based and IP-based GIDs. I have also created a git tree for our user-level driver [2]. Testing ======= We have tested this internally for various types of Guest OS - Red Hat, Centos, Ubuntu 12.04/14.04/16.04, Oracle Enterprise Linux, SLES 12 using backported versions of this driver. The tests included several runs of the performance tests (included with OFED), Intel MPI PingPong benchmark on OpenMPI, krping for FRWRs. Mellanox has been kind enough to test the backported version of the driver internally on their hardware using a VMware provided ESX build. I have also applied and tested this with Doug's k.o/for-4.9 branch (commit 5603910b). Note, that this patch series should be applied all together. I split out the commits so that it may be easier to review. PVRDMA Resources ================ [1] OFA Workshop Presentation - https://openfabrics.org/images/eventpresos/2016presentations/102parardma.pdf [2] Libpvrdma User-level library - http://git.openfabrics.org/?p=~aditr/libpvrdma.git;a=summary Reviewed-by: Jorgen Hansen <jhansen@vmware.com> Reviewed-by: George Zhang <georgezhang@vmware.com> Reviewed-by: Aditya Sarwade <asarwade@vmware.com> Reviewed-by: Bryan Tan <bryantan@vmware.com> Reviewed-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Adit Ranadive <aditr@vmware.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
587 lines
15 KiB
C
587 lines
15 KiB
C
/*
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* Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of EITHER the GNU General Public License
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* version 2 as published by the Free Software Foundation or the BSD
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* 2-Clause License. This program is distributed in the hope that it
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* will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
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* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License version 2 for more details at
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program available in the file COPYING in the main
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* directory of this source tree.
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*
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* The BSD 2-Clause License
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PVRDMA_DEV_API_H__
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#define __PVRDMA_DEV_API_H__
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#include <linux/types.h>
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#include "pvrdma_verbs.h"
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#define PVRDMA_VERSION 17
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#define PVRDMA_BOARD_ID 1
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#define PVRDMA_REV_ID 1
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/*
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* Masks and accessors for page directory, which is a two-level lookup:
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* page directory -> page table -> page. Only one directory for now, but we
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* could expand that easily. 9 bits for tables, 9 bits for pages, gives one
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* gigabyte for memory regions and so forth.
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*/
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#define PVRDMA_PDIR_SHIFT 18
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#define PVRDMA_PTABLE_SHIFT 9
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#define PVRDMA_PAGE_DIR_DIR(x) (((x) >> PVRDMA_PDIR_SHIFT) & 0x1)
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#define PVRDMA_PAGE_DIR_TABLE(x) (((x) >> PVRDMA_PTABLE_SHIFT) & 0x1ff)
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#define PVRDMA_PAGE_DIR_PAGE(x) ((x) & 0x1ff)
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#define PVRDMA_PAGE_DIR_MAX_PAGES (1 * 512 * 512)
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#define PVRDMA_MAX_FAST_REG_PAGES 128
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/*
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* Max MSI-X vectors.
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*/
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#define PVRDMA_MAX_INTERRUPTS 3
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/* Register offsets within PCI resource on BAR1. */
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#define PVRDMA_REG_VERSION 0x00 /* R: Version of device. */
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#define PVRDMA_REG_DSRLOW 0x04 /* W: Device shared region low PA. */
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#define PVRDMA_REG_DSRHIGH 0x08 /* W: Device shared region high PA. */
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#define PVRDMA_REG_CTL 0x0c /* W: PVRDMA_DEVICE_CTL */
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#define PVRDMA_REG_REQUEST 0x10 /* W: Indicate device request. */
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#define PVRDMA_REG_ERR 0x14 /* R: Device error. */
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#define PVRDMA_REG_ICR 0x18 /* R: Interrupt cause. */
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#define PVRDMA_REG_IMR 0x1c /* R/W: Interrupt mask. */
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#define PVRDMA_REG_MACL 0x20 /* R/W: MAC address low. */
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#define PVRDMA_REG_MACH 0x24 /* R/W: MAC address high. */
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/* Object flags. */
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#define PVRDMA_CQ_FLAG_ARMED_SOL BIT(0) /* Armed for solicited-only. */
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#define PVRDMA_CQ_FLAG_ARMED BIT(1) /* Armed. */
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#define PVRDMA_MR_FLAG_DMA BIT(0) /* DMA region. */
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#define PVRDMA_MR_FLAG_FRMR BIT(1) /* Fast reg memory region. */
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/*
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* Atomic operation capability (masked versions are extended atomic
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* operations.
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*/
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#define PVRDMA_ATOMIC_OP_COMP_SWAP BIT(0) /* Compare and swap. */
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#define PVRDMA_ATOMIC_OP_FETCH_ADD BIT(1) /* Fetch and add. */
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#define PVRDMA_ATOMIC_OP_MASK_COMP_SWAP BIT(2) /* Masked compare and swap. */
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#define PVRDMA_ATOMIC_OP_MASK_FETCH_ADD BIT(3) /* Masked fetch and add. */
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/*
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* Base Memory Management Extension flags to support Fast Reg Memory Regions
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* and Fast Reg Work Requests. Each flag represents a verb operation and we
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* must support all of them to qualify for the BMME device cap.
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*/
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#define PVRDMA_BMME_FLAG_LOCAL_INV BIT(0) /* Local Invalidate. */
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#define PVRDMA_BMME_FLAG_REMOTE_INV BIT(1) /* Remote Invalidate. */
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#define PVRDMA_BMME_FLAG_FAST_REG_WR BIT(2) /* Fast Reg Work Request. */
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/*
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* GID types. The interpretation of the gid_types bit field in the device
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* capabilities will depend on the device mode. For now, the device only
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* supports RoCE as mode, so only the different GID types for RoCE are
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* defined.
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*/
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#define PVRDMA_GID_TYPE_FLAG_ROCE_V1 BIT(0)
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#define PVRDMA_GID_TYPE_FLAG_ROCE_V2 BIT(1)
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enum pvrdma_pci_resource {
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PVRDMA_PCI_RESOURCE_MSIX, /* BAR0: MSI-X, MMIO. */
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PVRDMA_PCI_RESOURCE_REG, /* BAR1: Registers, MMIO. */
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PVRDMA_PCI_RESOURCE_UAR, /* BAR2: UAR pages, MMIO, 64-bit. */
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PVRDMA_PCI_RESOURCE_LAST, /* Last. */
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};
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enum pvrdma_device_ctl {
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PVRDMA_DEVICE_CTL_ACTIVATE, /* Activate device. */
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PVRDMA_DEVICE_CTL_QUIESCE, /* Quiesce device. */
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PVRDMA_DEVICE_CTL_RESET, /* Reset device. */
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};
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enum pvrdma_intr_vector {
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PVRDMA_INTR_VECTOR_RESPONSE, /* Command response. */
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PVRDMA_INTR_VECTOR_ASYNC, /* Async events. */
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PVRDMA_INTR_VECTOR_CQ, /* CQ notification. */
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/* Additional CQ notification vectors. */
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};
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enum pvrdma_intr_cause {
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PVRDMA_INTR_CAUSE_RESPONSE = (1 << PVRDMA_INTR_VECTOR_RESPONSE),
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PVRDMA_INTR_CAUSE_ASYNC = (1 << PVRDMA_INTR_VECTOR_ASYNC),
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PVRDMA_INTR_CAUSE_CQ = (1 << PVRDMA_INTR_VECTOR_CQ),
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};
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enum pvrdma_intr_type {
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PVRDMA_INTR_TYPE_INTX, /* Legacy. */
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PVRDMA_INTR_TYPE_MSI, /* MSI. */
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PVRDMA_INTR_TYPE_MSIX, /* MSI-X. */
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};
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enum pvrdma_gos_bits {
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PVRDMA_GOS_BITS_UNK, /* Unknown. */
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PVRDMA_GOS_BITS_32, /* 32-bit. */
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PVRDMA_GOS_BITS_64, /* 64-bit. */
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};
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enum pvrdma_gos_type {
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PVRDMA_GOS_TYPE_UNK, /* Unknown. */
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PVRDMA_GOS_TYPE_LINUX, /* Linux. */
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};
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enum pvrdma_device_mode {
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PVRDMA_DEVICE_MODE_ROCE, /* RoCE. */
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PVRDMA_DEVICE_MODE_IWARP, /* iWarp. */
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PVRDMA_DEVICE_MODE_IB, /* InfiniBand. */
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};
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struct pvrdma_gos_info {
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u32 gos_bits:2; /* W: PVRDMA_GOS_BITS_ */
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u32 gos_type:4; /* W: PVRDMA_GOS_TYPE_ */
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u32 gos_ver:16; /* W: Guest OS version. */
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u32 gos_misc:10; /* W: Other. */
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u32 pad; /* Pad to 8-byte alignment. */
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};
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struct pvrdma_device_caps {
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u64 fw_ver; /* R: Query device. */
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__be64 node_guid;
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__be64 sys_image_guid;
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u64 max_mr_size;
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u64 page_size_cap;
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u64 atomic_arg_sizes; /* EX verbs. */
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u32 ex_comp_mask; /* EX verbs. */
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u32 device_cap_flags2; /* EX verbs. */
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u32 max_fa_bit_boundary; /* EX verbs. */
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u32 log_max_atomic_inline_arg; /* EX verbs. */
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u32 vendor_id;
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u32 vendor_part_id;
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u32 hw_ver;
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u32 max_qp;
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u32 max_qp_wr;
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u32 device_cap_flags;
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u32 max_sge;
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u32 max_sge_rd;
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u32 max_cq;
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u32 max_cqe;
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u32 max_mr;
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u32 max_pd;
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u32 max_qp_rd_atom;
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u32 max_ee_rd_atom;
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u32 max_res_rd_atom;
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u32 max_qp_init_rd_atom;
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u32 max_ee_init_rd_atom;
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u32 max_ee;
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u32 max_rdd;
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u32 max_mw;
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u32 max_raw_ipv6_qp;
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u32 max_raw_ethy_qp;
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u32 max_mcast_grp;
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u32 max_mcast_qp_attach;
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u32 max_total_mcast_qp_attach;
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u32 max_ah;
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u32 max_fmr;
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u32 max_map_per_fmr;
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u32 max_srq;
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u32 max_srq_wr;
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u32 max_srq_sge;
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u32 max_uar;
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u32 gid_tbl_len;
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u16 max_pkeys;
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u8 local_ca_ack_delay;
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u8 phys_port_cnt;
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u8 mode; /* PVRDMA_DEVICE_MODE_ */
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u8 atomic_ops; /* PVRDMA_ATOMIC_OP_* bits */
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u8 bmme_flags; /* FRWR Mem Mgmt Extensions */
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u8 gid_types; /* PVRDMA_GID_TYPE_FLAG_ */
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u8 reserved[4];
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};
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struct pvrdma_ring_page_info {
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u32 num_pages; /* Num pages incl. header. */
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u32 reserved; /* Reserved. */
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u64 pdir_dma; /* Page directory PA. */
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};
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#pragma pack(push, 1)
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struct pvrdma_device_shared_region {
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u32 driver_version; /* W: Driver version. */
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u32 pad; /* Pad to 8-byte align. */
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struct pvrdma_gos_info gos_info; /* W: Guest OS information. */
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u64 cmd_slot_dma; /* W: Command slot address. */
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u64 resp_slot_dma; /* W: Response slot address. */
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struct pvrdma_ring_page_info async_ring_pages;
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/* W: Async ring page info. */
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struct pvrdma_ring_page_info cq_ring_pages;
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/* W: CQ ring page info. */
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u32 uar_pfn; /* W: UAR pageframe. */
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u32 pad2; /* Pad to 8-byte align. */
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struct pvrdma_device_caps caps; /* R: Device capabilities. */
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};
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#pragma pack(pop)
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/* Event types. Currently a 1:1 mapping with enum ib_event. */
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enum pvrdma_eqe_type {
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PVRDMA_EVENT_CQ_ERR,
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PVRDMA_EVENT_QP_FATAL,
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PVRDMA_EVENT_QP_REQ_ERR,
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PVRDMA_EVENT_QP_ACCESS_ERR,
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PVRDMA_EVENT_COMM_EST,
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PVRDMA_EVENT_SQ_DRAINED,
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PVRDMA_EVENT_PATH_MIG,
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PVRDMA_EVENT_PATH_MIG_ERR,
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PVRDMA_EVENT_DEVICE_FATAL,
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PVRDMA_EVENT_PORT_ACTIVE,
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PVRDMA_EVENT_PORT_ERR,
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PVRDMA_EVENT_LID_CHANGE,
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PVRDMA_EVENT_PKEY_CHANGE,
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PVRDMA_EVENT_SM_CHANGE,
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PVRDMA_EVENT_SRQ_ERR,
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PVRDMA_EVENT_SRQ_LIMIT_REACHED,
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PVRDMA_EVENT_QP_LAST_WQE_REACHED,
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PVRDMA_EVENT_CLIENT_REREGISTER,
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PVRDMA_EVENT_GID_CHANGE,
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};
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/* Event queue element. */
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struct pvrdma_eqe {
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u32 type; /* Event type. */
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u32 info; /* Handle, other. */
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};
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/* CQ notification queue element. */
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struct pvrdma_cqne {
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u32 info; /* Handle */
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};
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enum {
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PVRDMA_CMD_FIRST,
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PVRDMA_CMD_QUERY_PORT = PVRDMA_CMD_FIRST,
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PVRDMA_CMD_QUERY_PKEY,
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PVRDMA_CMD_CREATE_PD,
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PVRDMA_CMD_DESTROY_PD,
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PVRDMA_CMD_CREATE_MR,
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PVRDMA_CMD_DESTROY_MR,
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PVRDMA_CMD_CREATE_CQ,
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PVRDMA_CMD_RESIZE_CQ,
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PVRDMA_CMD_DESTROY_CQ,
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PVRDMA_CMD_CREATE_QP,
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PVRDMA_CMD_MODIFY_QP,
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PVRDMA_CMD_QUERY_QP,
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PVRDMA_CMD_DESTROY_QP,
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PVRDMA_CMD_CREATE_UC,
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PVRDMA_CMD_DESTROY_UC,
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PVRDMA_CMD_CREATE_BIND,
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PVRDMA_CMD_DESTROY_BIND,
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PVRDMA_CMD_MAX,
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};
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enum {
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PVRDMA_CMD_FIRST_RESP = (1 << 31),
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PVRDMA_CMD_QUERY_PORT_RESP = PVRDMA_CMD_FIRST_RESP,
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PVRDMA_CMD_QUERY_PKEY_RESP,
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PVRDMA_CMD_CREATE_PD_RESP,
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PVRDMA_CMD_DESTROY_PD_RESP_NOOP,
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PVRDMA_CMD_CREATE_MR_RESP,
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PVRDMA_CMD_DESTROY_MR_RESP_NOOP,
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PVRDMA_CMD_CREATE_CQ_RESP,
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PVRDMA_CMD_RESIZE_CQ_RESP,
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PVRDMA_CMD_DESTROY_CQ_RESP_NOOP,
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PVRDMA_CMD_CREATE_QP_RESP,
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PVRDMA_CMD_MODIFY_QP_RESP,
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PVRDMA_CMD_QUERY_QP_RESP,
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PVRDMA_CMD_DESTROY_QP_RESP,
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PVRDMA_CMD_CREATE_UC_RESP,
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PVRDMA_CMD_DESTROY_UC_RESP_NOOP,
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PVRDMA_CMD_CREATE_BIND_RESP_NOOP,
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PVRDMA_CMD_DESTROY_BIND_RESP_NOOP,
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PVRDMA_CMD_MAX_RESP,
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};
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struct pvrdma_cmd_hdr {
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u64 response; /* Key for response lookup. */
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u32 cmd; /* PVRDMA_CMD_ */
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u32 reserved; /* Reserved. */
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};
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struct pvrdma_cmd_resp_hdr {
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u64 response; /* From cmd hdr. */
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u32 ack; /* PVRDMA_CMD_XXX_RESP */
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u8 err; /* Error. */
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u8 reserved[3]; /* Reserved. */
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};
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struct pvrdma_cmd_query_port {
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struct pvrdma_cmd_hdr hdr;
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u8 port_num;
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u8 reserved[7];
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};
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struct pvrdma_cmd_query_port_resp {
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struct pvrdma_cmd_resp_hdr hdr;
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struct pvrdma_port_attr attrs;
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};
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struct pvrdma_cmd_query_pkey {
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struct pvrdma_cmd_hdr hdr;
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u8 port_num;
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u8 index;
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u8 reserved[6];
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};
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struct pvrdma_cmd_query_pkey_resp {
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struct pvrdma_cmd_resp_hdr hdr;
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u16 pkey;
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u8 reserved[6];
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};
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struct pvrdma_cmd_create_uc {
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struct pvrdma_cmd_hdr hdr;
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u32 pfn; /* UAR page frame number */
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u8 reserved[4];
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};
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struct pvrdma_cmd_create_uc_resp {
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struct pvrdma_cmd_resp_hdr hdr;
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u32 ctx_handle;
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u8 reserved[4];
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};
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struct pvrdma_cmd_destroy_uc {
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struct pvrdma_cmd_hdr hdr;
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u32 ctx_handle;
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u8 reserved[4];
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};
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struct pvrdma_cmd_create_pd {
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struct pvrdma_cmd_hdr hdr;
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u32 ctx_handle;
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u8 reserved[4];
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};
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struct pvrdma_cmd_create_pd_resp {
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struct pvrdma_cmd_resp_hdr hdr;
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u32 pd_handle;
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u8 reserved[4];
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};
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struct pvrdma_cmd_destroy_pd {
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struct pvrdma_cmd_hdr hdr;
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u32 pd_handle;
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u8 reserved[4];
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};
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struct pvrdma_cmd_create_mr {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u64 start;
|
|
u64 length;
|
|
u64 pdir_dma;
|
|
u32 pd_handle;
|
|
u32 access_flags;
|
|
u32 flags;
|
|
u32 nchunks;
|
|
};
|
|
|
|
struct pvrdma_cmd_create_mr_resp {
|
|
struct pvrdma_cmd_resp_hdr hdr;
|
|
u32 mr_handle;
|
|
u32 lkey;
|
|
u32 rkey;
|
|
u8 reserved[4];
|
|
};
|
|
|
|
struct pvrdma_cmd_destroy_mr {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u32 mr_handle;
|
|
u8 reserved[4];
|
|
};
|
|
|
|
struct pvrdma_cmd_create_cq {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u64 pdir_dma;
|
|
u32 ctx_handle;
|
|
u32 cqe;
|
|
u32 nchunks;
|
|
u8 reserved[4];
|
|
};
|
|
|
|
struct pvrdma_cmd_create_cq_resp {
|
|
struct pvrdma_cmd_resp_hdr hdr;
|
|
u32 cq_handle;
|
|
u32 cqe;
|
|
};
|
|
|
|
struct pvrdma_cmd_resize_cq {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u32 cq_handle;
|
|
u32 cqe;
|
|
};
|
|
|
|
struct pvrdma_cmd_resize_cq_resp {
|
|
struct pvrdma_cmd_resp_hdr hdr;
|
|
u32 cqe;
|
|
u8 reserved[4];
|
|
};
|
|
|
|
struct pvrdma_cmd_destroy_cq {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u32 cq_handle;
|
|
u8 reserved[4];
|
|
};
|
|
|
|
struct pvrdma_cmd_create_qp {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u64 pdir_dma;
|
|
u32 pd_handle;
|
|
u32 send_cq_handle;
|
|
u32 recv_cq_handle;
|
|
u32 srq_handle;
|
|
u32 max_send_wr;
|
|
u32 max_recv_wr;
|
|
u32 max_send_sge;
|
|
u32 max_recv_sge;
|
|
u32 max_inline_data;
|
|
u32 lkey;
|
|
u32 access_flags;
|
|
u16 total_chunks;
|
|
u16 send_chunks;
|
|
u16 max_atomic_arg;
|
|
u8 sq_sig_all;
|
|
u8 qp_type;
|
|
u8 is_srq;
|
|
u8 reserved[3];
|
|
};
|
|
|
|
struct pvrdma_cmd_create_qp_resp {
|
|
struct pvrdma_cmd_resp_hdr hdr;
|
|
u32 qpn;
|
|
u32 max_send_wr;
|
|
u32 max_recv_wr;
|
|
u32 max_send_sge;
|
|
u32 max_recv_sge;
|
|
u32 max_inline_data;
|
|
};
|
|
|
|
struct pvrdma_cmd_modify_qp {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u32 qp_handle;
|
|
u32 attr_mask;
|
|
struct pvrdma_qp_attr attrs;
|
|
};
|
|
|
|
struct pvrdma_cmd_query_qp {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u32 qp_handle;
|
|
u32 attr_mask;
|
|
};
|
|
|
|
struct pvrdma_cmd_query_qp_resp {
|
|
struct pvrdma_cmd_resp_hdr hdr;
|
|
struct pvrdma_qp_attr attrs;
|
|
};
|
|
|
|
struct pvrdma_cmd_destroy_qp {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u32 qp_handle;
|
|
u8 reserved[4];
|
|
};
|
|
|
|
struct pvrdma_cmd_destroy_qp_resp {
|
|
struct pvrdma_cmd_resp_hdr hdr;
|
|
u32 events_reported;
|
|
u8 reserved[4];
|
|
};
|
|
|
|
struct pvrdma_cmd_create_bind {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u32 mtu;
|
|
u32 vlan;
|
|
u32 index;
|
|
u8 new_gid[16];
|
|
u8 gid_type;
|
|
u8 reserved[3];
|
|
};
|
|
|
|
struct pvrdma_cmd_destroy_bind {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
u32 index;
|
|
u8 dest_gid[16];
|
|
u8 reserved[4];
|
|
};
|
|
|
|
union pvrdma_cmd_req {
|
|
struct pvrdma_cmd_hdr hdr;
|
|
struct pvrdma_cmd_query_port query_port;
|
|
struct pvrdma_cmd_query_pkey query_pkey;
|
|
struct pvrdma_cmd_create_uc create_uc;
|
|
struct pvrdma_cmd_destroy_uc destroy_uc;
|
|
struct pvrdma_cmd_create_pd create_pd;
|
|
struct pvrdma_cmd_destroy_pd destroy_pd;
|
|
struct pvrdma_cmd_create_mr create_mr;
|
|
struct pvrdma_cmd_destroy_mr destroy_mr;
|
|
struct pvrdma_cmd_create_cq create_cq;
|
|
struct pvrdma_cmd_resize_cq resize_cq;
|
|
struct pvrdma_cmd_destroy_cq destroy_cq;
|
|
struct pvrdma_cmd_create_qp create_qp;
|
|
struct pvrdma_cmd_modify_qp modify_qp;
|
|
struct pvrdma_cmd_query_qp query_qp;
|
|
struct pvrdma_cmd_destroy_qp destroy_qp;
|
|
struct pvrdma_cmd_create_bind create_bind;
|
|
struct pvrdma_cmd_destroy_bind destroy_bind;
|
|
};
|
|
|
|
union pvrdma_cmd_resp {
|
|
struct pvrdma_cmd_resp_hdr hdr;
|
|
struct pvrdma_cmd_query_port_resp query_port_resp;
|
|
struct pvrdma_cmd_query_pkey_resp query_pkey_resp;
|
|
struct pvrdma_cmd_create_uc_resp create_uc_resp;
|
|
struct pvrdma_cmd_create_pd_resp create_pd_resp;
|
|
struct pvrdma_cmd_create_mr_resp create_mr_resp;
|
|
struct pvrdma_cmd_create_cq_resp create_cq_resp;
|
|
struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
|
|
struct pvrdma_cmd_create_qp_resp create_qp_resp;
|
|
struct pvrdma_cmd_query_qp_resp query_qp_resp;
|
|
struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
|
|
};
|
|
|
|
#endif /* __PVRDMA_DEV_API_H__ */
|