![Anson Huang](/assets/img/avatar_default.png)
Add 696MHz operating point for i.MX6UL, only for those parts with speed grading fuse set to 2b'10 supports 696MHz operating point, so, speed grading check is also added for i.MX6UL in this patch, the clock tree for each operating point are as below: 696MHz: pll1 696000000 pll1_bypass 696000000 pll1_sys 696000000 pll1_sw 696000000 arm 696000000 528MHz: pll2 528000000 pll2_bypass 528000000 pll2_bus 528000000 ca7_secondary_sel 528000000 step 528000000 pll1_sw 528000000 arm 528000000 396MHz: pll2_pfd2_396m 396000000 ca7_secondary_sel 396000000 step 396000000 pll1_sw 396000000 arm 396000000 198MHz: pll2_pfd2_396m 396000000 ca7_secondary_sel 396000000 step 396000000 pll1_sw 396000000 arm 198000000 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
510 lines
14 KiB
C
510 lines
14 KiB
C
/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pm_opp.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#define PU_SOC_VOLTAGE_NORMAL 1250000
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#define PU_SOC_VOLTAGE_HIGH 1275000
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#define FREQ_1P2_GHZ 1200000000
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static struct regulator *arm_reg;
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static struct regulator *pu_reg;
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static struct regulator *soc_reg;
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enum IMX6_CPUFREQ_CLKS {
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ARM,
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PLL1_SYS,
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STEP,
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PLL1_SW,
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PLL2_PFD2_396M,
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/* MX6UL requires two more clks */
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PLL2_BUS,
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SECONDARY_SEL,
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};
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#define IMX6Q_CPUFREQ_CLK_NUM 5
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#define IMX6UL_CPUFREQ_CLK_NUM 7
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static int num_clks;
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static struct clk_bulk_data clks[] = {
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{ .id = "arm" },
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{ .id = "pll1_sys" },
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{ .id = "step" },
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{ .id = "pll1_sw" },
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{ .id = "pll2_pfd2_396m" },
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{ .id = "pll2_bus" },
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{ .id = "secondary_sel" },
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};
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static struct device *cpu_dev;
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static bool free_opp;
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static struct cpufreq_frequency_table *freq_table;
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static unsigned int transition_latency;
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static u32 *imx6_soc_volt;
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static u32 soc_opp_count;
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static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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{
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struct dev_pm_opp *opp;
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unsigned long freq_hz, volt, volt_old;
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unsigned int old_freq, new_freq;
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bool pll1_sys_temp_enabled = false;
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int ret;
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new_freq = freq_table[index].frequency;
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freq_hz = new_freq * 1000;
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old_freq = clk_get_rate(clks[ARM].clk) / 1000;
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
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if (IS_ERR(opp)) {
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dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
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return PTR_ERR(opp);
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}
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volt = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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volt_old = regulator_get_voltage(arm_reg);
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dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
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old_freq / 1000, volt_old / 1000,
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new_freq / 1000, volt / 1000);
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/* scaling up? scale voltage before frequency */
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if (new_freq > old_freq) {
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if (!IS_ERR(pu_reg)) {
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ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
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return ret;
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}
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}
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ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
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return ret;
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}
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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if (ret) {
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dev_err(cpu_dev,
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"failed to scale vddarm up: %d\n", ret);
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return ret;
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}
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}
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/*
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* The setpoints are selected per PLL/PDF frequencies, so we need to
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* reprogram PLL for frequency scaling. The procedure of reprogramming
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* PLL1 is as below.
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* For i.MX6UL, it has a secondary clk mux, the cpu frequency change
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* flow is slightly different from other i.MX6 OSC.
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* The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
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* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
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* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
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* - Disable pll2_pfd2_396m_clk
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*/
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if (of_machine_is_compatible("fsl,imx6ul") ||
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of_machine_is_compatible("fsl,imx6ull")) {
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/*
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* When changing pll1_sw_clk's parent to pll1_sys_clk,
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* CPU may run at higher than 528MHz, this will lead to
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* the system unstable if the voltage is lower than the
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* voltage of 528MHz, so lower the CPU frequency to one
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* half before changing CPU frequency.
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*/
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clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
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clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
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if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
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clk_set_parent(clks[SECONDARY_SEL].clk,
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clks[PLL2_BUS].clk);
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else
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clk_set_parent(clks[SECONDARY_SEL].clk,
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clks[PLL2_PFD2_396M].clk);
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clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
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clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
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if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
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clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
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clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
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}
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} else {
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clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
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clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
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if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
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clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
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clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
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} else {
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/* pll1_sys needs to be enabled for divider rate change to work. */
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pll1_sys_temp_enabled = true;
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clk_prepare_enable(clks[PLL1_SYS].clk);
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}
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}
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/* Ensure the arm clock divider is what we expect */
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ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
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if (ret) {
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dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
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regulator_set_voltage_tol(arm_reg, volt_old, 0);
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return ret;
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}
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/* PLL1 is only needed until after ARM-PODF is set. */
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if (pll1_sys_temp_enabled)
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clk_disable_unprepare(clks[PLL1_SYS].clk);
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/* scaling down? scale voltage after frequency */
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if (new_freq < old_freq) {
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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if (ret) {
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dev_warn(cpu_dev,
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"failed to scale vddarm down: %d\n", ret);
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ret = 0;
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}
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ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
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ret = 0;
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}
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if (!IS_ERR(pu_reg)) {
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ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
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ret = 0;
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}
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}
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}
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return 0;
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}
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static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
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{
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int ret;
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policy->clk = clks[ARM].clk;
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ret = cpufreq_generic_init(policy, freq_table, transition_latency);
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policy->suspend_freq = policy->max;
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return ret;
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}
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static struct cpufreq_driver imx6q_cpufreq_driver = {
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = imx6q_set_target,
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.get = cpufreq_generic_get,
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.init = imx6q_cpufreq_init,
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.name = "imx6q-cpufreq",
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.attr = cpufreq_generic_attr,
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.suspend = cpufreq_generic_suspend,
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};
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#define OCOTP_CFG3 0x440
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#define OCOTP_CFG3_SPEED_SHIFT 16
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#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
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#define OCOTP_CFG3_SPEED_996MHZ 0x2
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#define OCOTP_CFG3_SPEED_852MHZ 0x1
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static void imx6q_opp_check_speed_grading(struct device *dev)
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{
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struct device_node *np;
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void __iomem *base;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
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if (!np)
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return;
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base = of_iomap(np, 0);
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if (!base) {
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dev_err(dev, "failed to map ocotp\n");
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goto put_node;
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}
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/*
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* SPEED_GRADING[1:0] defines the max speed of ARM:
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* 2b'11: 1200000000Hz;
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* 2b'10: 996000000Hz;
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* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
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* 2b'00: 792000000Hz;
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* We need to set the max speed of ARM according to fuse map.
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*/
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val = readl_relaxed(base + OCOTP_CFG3);
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val >>= OCOTP_CFG3_SPEED_SHIFT;
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val &= 0x3;
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if (val < OCOTP_CFG3_SPEED_996MHZ)
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if (dev_pm_opp_disable(dev, 996000000))
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dev_warn(dev, "failed to disable 996MHz OPP\n");
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if (of_machine_is_compatible("fsl,imx6q") ||
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of_machine_is_compatible("fsl,imx6qp")) {
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if (val != OCOTP_CFG3_SPEED_852MHZ)
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if (dev_pm_opp_disable(dev, 852000000))
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dev_warn(dev, "failed to disable 852MHz OPP\n");
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if (val != OCOTP_CFG3_SPEED_1P2GHZ)
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if (dev_pm_opp_disable(dev, 1200000000))
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dev_warn(dev, "failed to disable 1.2GHz OPP\n");
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}
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iounmap(base);
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put_node:
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of_node_put(np);
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}
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#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
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static void imx6ul_opp_check_speed_grading(struct device *dev)
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{
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struct device_node *np;
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void __iomem *base;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
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if (!np)
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return;
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base = of_iomap(np, 0);
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if (!base) {
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dev_err(dev, "failed to map ocotp\n");
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goto put_node;
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}
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/*
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* Speed GRADING[1:0] defines the max speed of ARM:
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* 2b'00: Reserved;
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* 2b'01: 528000000Hz;
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* 2b'10: 696000000Hz;
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* 2b'11: Reserved;
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* We need to set the max speed of ARM according to fuse map.
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*/
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val = readl_relaxed(base + OCOTP_CFG3);
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val >>= OCOTP_CFG3_SPEED_SHIFT;
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val &= 0x3;
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if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
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if (dev_pm_opp_disable(dev, 696000000))
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dev_warn(dev, "failed to disable 696MHz OPP\n");
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iounmap(base);
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put_node:
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of_node_put(np);
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}
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static int imx6q_cpufreq_probe(struct platform_device *pdev)
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{
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struct device_node *np;
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struct dev_pm_opp *opp;
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unsigned long min_volt, max_volt;
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int num, ret;
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const struct property *prop;
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const __be32 *val;
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u32 nr, i, j;
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cpu_dev = get_cpu_device(0);
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if (!cpu_dev) {
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pr_err("failed to get cpu0 device\n");
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return -ENODEV;
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}
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np = of_node_get(cpu_dev->of_node);
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if (!np) {
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dev_err(cpu_dev, "failed to find cpu0 node\n");
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return -ENOENT;
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}
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if (of_machine_is_compatible("fsl,imx6ul") ||
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of_machine_is_compatible("fsl,imx6ull"))
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num_clks = IMX6UL_CPUFREQ_CLK_NUM;
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else
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num_clks = IMX6Q_CPUFREQ_CLK_NUM;
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ret = clk_bulk_get(cpu_dev, num_clks, clks);
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if (ret)
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goto put_node;
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arm_reg = regulator_get(cpu_dev, "arm");
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pu_reg = regulator_get_optional(cpu_dev, "pu");
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soc_reg = regulator_get(cpu_dev, "soc");
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if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
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PTR_ERR(soc_reg) == -EPROBE_DEFER ||
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PTR_ERR(pu_reg) == -EPROBE_DEFER) {
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ret = -EPROBE_DEFER;
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dev_dbg(cpu_dev, "regulators not ready, defer\n");
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goto put_reg;
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}
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if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
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dev_err(cpu_dev, "failed to get regulators\n");
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ret = -ENOENT;
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goto put_reg;
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}
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ret = dev_pm_opp_of_add_table(cpu_dev);
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if (ret < 0) {
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dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
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goto put_reg;
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}
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if (of_machine_is_compatible("fsl,imx6ul"))
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imx6ul_opp_check_speed_grading(cpu_dev);
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else
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imx6q_opp_check_speed_grading(cpu_dev);
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/* Because we have added the OPPs here, we must free them */
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free_opp = true;
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num = dev_pm_opp_get_opp_count(cpu_dev);
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if (num < 0) {
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ret = num;
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dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
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goto out_free_opp;
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}
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ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
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if (ret) {
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dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
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goto out_free_opp;
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}
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/* Make imx6_soc_volt array's size same as arm opp number */
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imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
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if (imx6_soc_volt == NULL) {
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ret = -ENOMEM;
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goto free_freq_table;
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}
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prop = of_find_property(np, "fsl,soc-operating-points", NULL);
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if (!prop || !prop->value)
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goto soc_opp_out;
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/*
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* Each OPP is a set of tuples consisting of frequency and
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* voltage like <freq-kHz vol-uV>.
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*/
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nr = prop->length / sizeof(u32);
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if (nr % 2 || (nr / 2) < num)
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goto soc_opp_out;
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for (j = 0; j < num; j++) {
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val = prop->value;
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for (i = 0; i < nr / 2; i++) {
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unsigned long freq = be32_to_cpup(val++);
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unsigned long volt = be32_to_cpup(val++);
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if (freq_table[j].frequency == freq) {
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imx6_soc_volt[soc_opp_count++] = volt;
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break;
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}
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}
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}
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soc_opp_out:
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/* use fixed soc opp volt if no valid soc opp info found in dtb */
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if (soc_opp_count != num) {
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dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
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for (j = 0; j < num; j++)
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imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
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if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
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imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
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}
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if (of_property_read_u32(np, "clock-latency", &transition_latency))
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transition_latency = CPUFREQ_ETERNAL;
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/*
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* Calculate the ramp time for max voltage change in the
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* VDDSOC and VDDPU regulators.
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*/
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ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
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if (ret > 0)
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transition_latency += ret * 1000;
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if (!IS_ERR(pu_reg)) {
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ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
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if (ret > 0)
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transition_latency += ret * 1000;
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}
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/*
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* OPP is maintained in order of increasing frequency, and
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* freq_table initialised from OPP is therefore sorted in the
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* same order.
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*/
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opp = dev_pm_opp_find_freq_exact(cpu_dev,
|
|
freq_table[0].frequency * 1000, true);
|
|
min_volt = dev_pm_opp_get_voltage(opp);
|
|
dev_pm_opp_put(opp);
|
|
opp = dev_pm_opp_find_freq_exact(cpu_dev,
|
|
freq_table[--num].frequency * 1000, true);
|
|
max_volt = dev_pm_opp_get_voltage(opp);
|
|
dev_pm_opp_put(opp);
|
|
|
|
ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
|
|
if (ret > 0)
|
|
transition_latency += ret * 1000;
|
|
|
|
ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
|
|
if (ret) {
|
|
dev_err(cpu_dev, "failed register driver: %d\n", ret);
|
|
goto free_freq_table;
|
|
}
|
|
|
|
of_node_put(np);
|
|
return 0;
|
|
|
|
free_freq_table:
|
|
dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
|
|
out_free_opp:
|
|
if (free_opp)
|
|
dev_pm_opp_of_remove_table(cpu_dev);
|
|
put_reg:
|
|
if (!IS_ERR(arm_reg))
|
|
regulator_put(arm_reg);
|
|
if (!IS_ERR(pu_reg))
|
|
regulator_put(pu_reg);
|
|
if (!IS_ERR(soc_reg))
|
|
regulator_put(soc_reg);
|
|
|
|
clk_bulk_put(num_clks, clks);
|
|
put_node:
|
|
of_node_put(np);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int imx6q_cpufreq_remove(struct platform_device *pdev)
|
|
{
|
|
cpufreq_unregister_driver(&imx6q_cpufreq_driver);
|
|
dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
|
|
if (free_opp)
|
|
dev_pm_opp_of_remove_table(cpu_dev);
|
|
regulator_put(arm_reg);
|
|
if (!IS_ERR(pu_reg))
|
|
regulator_put(pu_reg);
|
|
regulator_put(soc_reg);
|
|
|
|
clk_bulk_put(num_clks, clks);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver imx6q_cpufreq_platdrv = {
|
|
.driver = {
|
|
.name = "imx6q-cpufreq",
|
|
},
|
|
.probe = imx6q_cpufreq_probe,
|
|
.remove = imx6q_cpufreq_remove,
|
|
};
|
|
module_platform_driver(imx6q_cpufreq_platdrv);
|
|
|
|
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
|
|
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
|
|
MODULE_LICENSE("GPL");
|