![Marek Szyprowski](/assets/img/avatar_default.png)
Some CRTC drivers (like Exynos DRM Mixer) can handle blocking register updates only on per-device level, not per-plane level. This patch changes exynos_crts atomic_begin/atomic_flush callbacks to handle the entire crtc, instead of given planes, so driver can handle both cases on their own. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
726 lines
18 KiB
C
726 lines
18 KiB
C
/* drivers/gpu/drm/exynos5433_drm_decon.c
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*
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* Copyright (C) 2015 Samsung Electronics Co.Ltd
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* Authors:
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* Joonyoung Shim <jy0922.shim@samsung.com>
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* Hyungwon Hwang <human.hwang@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundationr
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*/
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/pm_runtime.h>
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#include <video/exynos5433_decon.h>
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#include "exynos_drm_drv.h"
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#include "exynos_drm_crtc.h"
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#include "exynos_drm_fb.h"
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#include "exynos_drm_plane.h"
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#include "exynos_drm_iommu.h"
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#define WINDOWS_NR 3
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#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
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static const char * const decon_clks_name[] = {
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"pclk",
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"aclk_decon",
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"aclk_smmu_decon0x",
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"aclk_xiu_decon0x",
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"pclk_smmu_decon0x",
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"sclk_decon_vclk",
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"sclk_decon_eclk",
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};
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enum decon_iftype {
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IFTYPE_RGB,
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IFTYPE_I80,
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IFTYPE_HDMI
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};
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enum decon_flag_bits {
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BIT_CLKS_ENABLED,
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BIT_IRQS_ENABLED,
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BIT_WIN_UPDATED,
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BIT_SUSPENDED
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};
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struct decon_context {
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struct device *dev;
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struct drm_device *drm_dev;
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struct exynos_drm_crtc *crtc;
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struct exynos_drm_plane planes[WINDOWS_NR];
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struct exynos_drm_plane_config configs[WINDOWS_NR];
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void __iomem *addr;
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struct clk *clks[ARRAY_SIZE(decon_clks_name)];
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int pipe;
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unsigned long flags;
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enum decon_iftype out_type;
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int first_win;
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};
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static const uint32_t decon_formats[] = {
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DRM_FORMAT_XRGB1555,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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};
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static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
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DRM_PLANE_TYPE_PRIMARY,
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DRM_PLANE_TYPE_OVERLAY,
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DRM_PLANE_TYPE_CURSOR,
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};
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static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
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u32 val)
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{
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val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
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writel(val, ctx->addr + reg);
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}
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static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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u32 val;
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return -EPERM;
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if (test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
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val = VIDINTCON0_INTEN;
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if (ctx->out_type == IFTYPE_I80)
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val |= VIDINTCON0_FRAMEDONE;
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else
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val |= VIDINTCON0_INTFRMEN;
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writel(val, ctx->addr + DECON_VIDINTCON0);
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}
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return 0;
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}
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static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
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writel(0, ctx->addr + DECON_VIDINTCON0);
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}
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static void decon_setup_trigger(struct decon_context *ctx)
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{
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u32 val = (ctx->out_type != IFTYPE_HDMI)
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? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
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TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
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: TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
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TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
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writel(val, ctx->addr + DECON_TRIGCON);
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}
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static void decon_commit(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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struct drm_display_mode *m = &crtc->base.mode;
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u32 val;
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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if (ctx->out_type == IFTYPE_HDMI) {
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m->crtc_hsync_start = m->crtc_hdisplay + 10;
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m->crtc_hsync_end = m->crtc_htotal - 92;
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m->crtc_vsync_start = m->crtc_vdisplay + 1;
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m->crtc_vsync_end = m->crtc_vsync_start + 1;
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}
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decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
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/* enable clock gate */
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val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
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writel(val, ctx->addr + DECON_CMU);
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/* lcd on and use command if */
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val = VIDOUT_LCD_ON;
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if (ctx->out_type == IFTYPE_I80)
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val |= VIDOUT_COMMAND_IF;
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else
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val |= VIDOUT_RGB_IF;
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writel(val, ctx->addr + DECON_VIDOUTCON0);
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val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
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VIDTCON2_HOZVAL(m->hdisplay - 1);
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writel(val, ctx->addr + DECON_VIDTCON2);
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if (ctx->out_type != IFTYPE_I80) {
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val = VIDTCON00_VBPD_F(
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m->crtc_vtotal - m->crtc_vsync_end - 1) |
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VIDTCON00_VFPD_F(
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m->crtc_vsync_start - m->crtc_vdisplay - 1);
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writel(val, ctx->addr + DECON_VIDTCON00);
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val = VIDTCON01_VSPW_F(
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m->crtc_vsync_end - m->crtc_vsync_start - 1);
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writel(val, ctx->addr + DECON_VIDTCON01);
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val = VIDTCON10_HBPD_F(
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m->crtc_htotal - m->crtc_hsync_end - 1) |
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VIDTCON10_HFPD_F(
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m->crtc_hsync_start - m->crtc_hdisplay - 1);
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writel(val, ctx->addr + DECON_VIDTCON10);
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val = VIDTCON11_HSPW_F(
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m->crtc_hsync_end - m->crtc_hsync_start - 1);
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writel(val, ctx->addr + DECON_VIDTCON11);
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}
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decon_setup_trigger(ctx);
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/* enable output and display signal */
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decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
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}
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static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
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struct drm_framebuffer *fb)
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{
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unsigned long val;
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val = readl(ctx->addr + DECON_WINCONx(win));
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val &= ~WINCONx_BPPMODE_MASK;
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switch (fb->pixel_format) {
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case DRM_FORMAT_XRGB1555:
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val |= WINCONx_BPPMODE_16BPP_I1555;
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val |= WINCONx_HAWSWP_F;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_RGB565:
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val |= WINCONx_BPPMODE_16BPP_565;
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val |= WINCONx_HAWSWP_F;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_XRGB8888:
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val |= WINCONx_BPPMODE_24BPP_888;
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val |= WINCONx_WSWP_F;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_ARGB8888:
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val |= WINCONx_BPPMODE_32BPP_A8888;
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val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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default:
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DRM_ERROR("Proper pixel format is not set\n");
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return;
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}
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DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
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/*
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* In case of exynos, setting dma-burst to 16Word causes permanent
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* tearing for very small buffers, e.g. cursor buffer. Burst Mode
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* switching which is based on plane size is not recommended as
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* plane size varies a lot towards the end of the screen and rapid
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* movement causes unstable DMA which results into iommu crash/tear.
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*/
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if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
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val &= ~WINCONx_BURSTLEN_MASK;
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val |= WINCONx_BURSTLEN_8WORD;
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}
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writel(val, ctx->addr + DECON_WINCONx(win));
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}
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static void decon_shadow_protect_win(struct decon_context *ctx, int win,
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bool protect)
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{
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decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
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protect ? ~0 : 0);
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}
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static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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int i;
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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for (i = ctx->first_win; i < WINDOWS_NR; i++)
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decon_shadow_protect_win(ctx, i, true);
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}
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#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
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#define COORDINATE_X(x) BIT_VAL((x), 23, 12)
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#define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
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static void decon_update_plane(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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struct exynos_drm_plane_state *state =
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to_exynos_plane_state(plane->base.state);
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struct decon_context *ctx = crtc->ctx;
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struct drm_framebuffer *fb = state->base.fb;
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unsigned int win = plane->index;
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unsigned int bpp = fb->bits_per_pixel >> 3;
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unsigned int pitch = fb->pitches[0];
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dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
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u32 val;
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
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writel(val, ctx->addr + DECON_VIDOSDxA(win));
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val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
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COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
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writel(val, ctx->addr + DECON_VIDOSDxB(win));
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val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
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VIDOSD_Wx_ALPHA_B_F(0x0);
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writel(val, ctx->addr + DECON_VIDOSDxC(win));
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val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
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VIDOSD_Wx_ALPHA_B_F(0x0);
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writel(val, ctx->addr + DECON_VIDOSDxD(win));
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writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
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val = dma_addr + pitch * state->src.h;
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writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
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if (ctx->out_type != IFTYPE_HDMI)
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val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
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| BIT_VAL(state->crtc.w * bpp, 13, 0);
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else
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val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
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| BIT_VAL(state->crtc.w * bpp, 14, 0);
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writel(val, ctx->addr + DECON_VIDW0xADD2(win));
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decon_win_set_pixfmt(ctx, win, fb);
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/* window enable */
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decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
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/* standalone update */
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decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
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}
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static void decon_disable_plane(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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struct decon_context *ctx = crtc->ctx;
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unsigned int win = plane->index;
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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decon_shadow_protect_win(ctx, win, true);
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/* window disable */
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decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
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decon_shadow_protect_win(ctx, win, false);
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/* standalone update */
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decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
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}
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static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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int i;
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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for (i = ctx->first_win; i < WINDOWS_NR; i++)
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decon_shadow_protect_win(ctx, i, false);
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if (ctx->out_type == IFTYPE_I80)
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set_bit(BIT_WIN_UPDATED, &ctx->flags);
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}
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static void decon_swreset(struct decon_context *ctx)
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{
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unsigned int tries;
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writel(0, ctx->addr + DECON_VIDCON0);
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for (tries = 2000; tries; --tries) {
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if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
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break;
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udelay(10);
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}
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WARN(tries == 0, "failed to disable DECON\n");
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writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
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for (tries = 2000; tries; --tries) {
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if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
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break;
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udelay(10);
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}
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WARN(tries == 0, "failed to software reset DECON\n");
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if (ctx->out_type != IFTYPE_HDMI)
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return;
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writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
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decon_set_bits(ctx, DECON_CMU,
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CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
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writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
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writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
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ctx->addr + DECON_CRCCTRL);
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decon_setup_trigger(ctx);
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}
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static void decon_enable(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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pm_runtime_get_sync(ctx->dev);
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set_bit(BIT_CLKS_ENABLED, &ctx->flags);
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/* if vblank was enabled status, enable it again. */
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if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
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decon_enable_vblank(ctx->crtc);
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decon_commit(ctx->crtc);
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set_bit(BIT_SUSPENDED, &ctx->flags);
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}
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static void decon_disable(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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int i;
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if (test_bit(BIT_SUSPENDED, &ctx->flags))
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return;
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/*
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* We need to make sure that all windows are disabled before we
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* suspend that connector. Otherwise we might try to scan from
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* a destroyed buffer later.
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*/
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for (i = ctx->first_win; i < WINDOWS_NR; i++)
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decon_disable_plane(crtc, &ctx->planes[i]);
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decon_swreset(ctx);
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clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
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pm_runtime_put_sync(ctx->dev);
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set_bit(BIT_SUSPENDED, &ctx->flags);
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}
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void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
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return;
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if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
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decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
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drm_crtc_handle_vblank(&ctx->crtc->base);
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}
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static void decon_clear_channels(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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int win, i, ret;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
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ret = clk_prepare_enable(ctx->clks[i]);
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if (ret < 0)
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goto err;
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|
}
|
|
|
|
for (win = 0; win < WINDOWS_NR; win++) {
|
|
decon_shadow_protect_win(ctx, win, true);
|
|
decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
|
|
decon_shadow_protect_win(ctx, win, false);
|
|
decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
|
|
}
|
|
/* TODO: wait for possible vsync */
|
|
msleep(50);
|
|
|
|
err:
|
|
while (--i >= 0)
|
|
clk_disable_unprepare(ctx->clks[i]);
|
|
}
|
|
|
|
static struct exynos_drm_crtc_ops decon_crtc_ops = {
|
|
.enable = decon_enable,
|
|
.disable = decon_disable,
|
|
.enable_vblank = decon_enable_vblank,
|
|
.disable_vblank = decon_disable_vblank,
|
|
.atomic_begin = decon_atomic_begin,
|
|
.update_plane = decon_update_plane,
|
|
.disable_plane = decon_disable_plane,
|
|
.atomic_flush = decon_atomic_flush,
|
|
.te_handler = decon_te_irq_handler,
|
|
};
|
|
|
|
static int decon_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct decon_context *ctx = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = data;
|
|
struct exynos_drm_private *priv = drm_dev->dev_private;
|
|
struct exynos_drm_plane *exynos_plane;
|
|
enum exynos_drm_output_type out_type;
|
|
unsigned int win;
|
|
int ret;
|
|
|
|
ctx->drm_dev = drm_dev;
|
|
ctx->pipe = priv->pipe++;
|
|
|
|
for (win = ctx->first_win; win < WINDOWS_NR; win++) {
|
|
int tmp = (win == ctx->first_win) ? 0 : win;
|
|
|
|
ctx->configs[win].pixel_formats = decon_formats;
|
|
ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
|
|
ctx->configs[win].zpos = win;
|
|
ctx->configs[win].type = decon_win_types[tmp];
|
|
|
|
ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
|
|
1 << ctx->pipe, &ctx->configs[win]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
exynos_plane = &ctx->planes[ctx->first_win];
|
|
out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
|
|
: EXYNOS_DISPLAY_TYPE_LCD;
|
|
ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
|
|
ctx->pipe, out_type,
|
|
&decon_crtc_ops, ctx);
|
|
if (IS_ERR(ctx->crtc)) {
|
|
ret = PTR_ERR(ctx->crtc);
|
|
goto err;
|
|
}
|
|
|
|
decon_clear_channels(ctx->crtc);
|
|
|
|
ret = drm_iommu_attach_device(drm_dev, dev);
|
|
if (ret)
|
|
goto err;
|
|
|
|
return ret;
|
|
err:
|
|
priv->pipe--;
|
|
return ret;
|
|
}
|
|
|
|
static void decon_unbind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct decon_context *ctx = dev_get_drvdata(dev);
|
|
|
|
decon_disable(ctx->crtc);
|
|
|
|
/* detach this sub driver from iommu mapping if supported. */
|
|
drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
|
|
}
|
|
|
|
static const struct component_ops decon_component_ops = {
|
|
.bind = decon_bind,
|
|
.unbind = decon_unbind,
|
|
};
|
|
|
|
static irqreturn_t decon_irq_handler(int irq, void *dev_id)
|
|
{
|
|
struct decon_context *ctx = dev_id;
|
|
u32 val;
|
|
int win;
|
|
|
|
if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
|
|
goto out;
|
|
|
|
val = readl(ctx->addr + DECON_VIDINTCON1);
|
|
val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
|
|
|
|
if (val) {
|
|
for (win = ctx->first_win; win < WINDOWS_NR ; win++) {
|
|
struct exynos_drm_plane *plane = &ctx->planes[win];
|
|
|
|
if (!plane->pending_fb)
|
|
continue;
|
|
|
|
exynos_drm_crtc_finish_update(ctx->crtc, plane);
|
|
}
|
|
|
|
/* clear */
|
|
writel(val, ctx->addr + DECON_VIDINTCON1);
|
|
}
|
|
|
|
out:
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int exynos5433_decon_suspend(struct device *dev)
|
|
{
|
|
struct decon_context *ctx = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++)
|
|
clk_disable_unprepare(ctx->clks[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos5433_decon_resume(struct device *dev)
|
|
{
|
|
struct decon_context *ctx = dev_get_drvdata(dev);
|
|
int i, ret;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
|
|
ret = clk_prepare_enable(ctx->clks[i]);
|
|
if (ret < 0)
|
|
goto err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
while (--i >= 0)
|
|
clk_disable_unprepare(ctx->clks[i]);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops exynos5433_decon_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
|
|
NULL)
|
|
};
|
|
|
|
static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
|
|
{
|
|
.compatible = "samsung,exynos5433-decon",
|
|
.data = (void *)IFTYPE_RGB
|
|
},
|
|
{
|
|
.compatible = "samsung,exynos5433-decon-tv",
|
|
.data = (void *)IFTYPE_HDMI
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
|
|
|
|
static int exynos5433_decon_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *of_id;
|
|
struct device *dev = &pdev->dev;
|
|
struct decon_context *ctx;
|
|
struct resource *res;
|
|
int ret;
|
|
int i;
|
|
|
|
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
|
if (!ctx)
|
|
return -ENOMEM;
|
|
|
|
__set_bit(BIT_SUSPENDED, &ctx->flags);
|
|
ctx->dev = dev;
|
|
|
|
of_id = of_match_device(exynos5433_decon_driver_dt_match, &pdev->dev);
|
|
ctx->out_type = (enum decon_iftype)of_id->data;
|
|
|
|
if (ctx->out_type == IFTYPE_HDMI)
|
|
ctx->first_win = 1;
|
|
else if (of_get_child_by_name(dev->of_node, "i80-if-timings"))
|
|
ctx->out_type = IFTYPE_I80;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
|
|
struct clk *clk;
|
|
|
|
clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
ctx->clks[i] = clk;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(dev, "cannot find IO resource\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
ctx->addr = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(ctx->addr)) {
|
|
dev_err(dev, "ioremap failed\n");
|
|
return PTR_ERR(ctx->addr);
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
|
|
(ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync");
|
|
if (!res) {
|
|
dev_err(dev, "cannot find IRQ resource\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
|
|
"drm_decon", ctx);
|
|
if (ret < 0) {
|
|
dev_err(dev, "lcd_sys irq request failed\n");
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, ctx);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
ret = component_add(dev, &decon_component_ops);
|
|
if (ret)
|
|
goto err_disable_pm_runtime;
|
|
|
|
return 0;
|
|
|
|
err_disable_pm_runtime:
|
|
pm_runtime_disable(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int exynos5433_decon_remove(struct platform_device *pdev)
|
|
{
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
component_del(&pdev->dev, &decon_component_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct platform_driver exynos5433_decon_driver = {
|
|
.probe = exynos5433_decon_probe,
|
|
.remove = exynos5433_decon_remove,
|
|
.driver = {
|
|
.name = "exynos5433-decon",
|
|
.pm = &exynos5433_decon_pm_ops,
|
|
.of_match_table = exynos5433_decon_driver_dt_match,
|
|
},
|
|
};
|