![Marek Szyprowski](/assets/img/avatar_default.png)
Some CRTC drivers (like Exynos DRM Mixer) can handle blocking register updates only on per-device level, not per-plane level. This patch changes exynos_crts atomic_begin/atomic_flush callbacks to handle the entire crtc, instead of given planes, so driver can handle both cases on their own. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
873 lines
21 KiB
C
873 lines
21 KiB
C
/* drivers/gpu/drm/exynos/exynos7_drm_decon.c
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*
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* Copyright (C) 2014 Samsung Electronics Co.Ltd
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* Authors:
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* Akshu Agarwal <akshua@gmail.com>
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* Ajay Kumar <ajaykumar.rs@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <drm/drmP.h>
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#include <drm/exynos_drm.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <video/of_display_timing.h>
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#include <video/of_videomode.h>
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#include <video/exynos7_decon.h>
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#include "exynos_drm_crtc.h"
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#include "exynos_drm_plane.h"
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#include "exynos_drm_drv.h"
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#include "exynos_drm_fb.h"
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#include "exynos_drm_fbdev.h"
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#include "exynos_drm_iommu.h"
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/*
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* DECON stands for Display and Enhancement controller.
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*/
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#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
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#define WINDOWS_NR 2
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struct decon_context {
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struct device *dev;
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struct drm_device *drm_dev;
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struct exynos_drm_crtc *crtc;
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struct exynos_drm_plane planes[WINDOWS_NR];
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struct exynos_drm_plane_config configs[WINDOWS_NR];
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struct clk *pclk;
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struct clk *aclk;
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struct clk *eclk;
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struct clk *vclk;
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void __iomem *regs;
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unsigned long irq_flags;
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bool i80_if;
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bool suspended;
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int pipe;
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wait_queue_head_t wait_vsync_queue;
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atomic_t wait_vsync_event;
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struct exynos_drm_panel_info panel;
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struct drm_encoder *encoder;
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};
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static const struct of_device_id decon_driver_dt_match[] = {
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{.compatible = "samsung,exynos7-decon"},
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{},
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};
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MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
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static const uint32_t decon_formats[] = {
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DRM_FORMAT_RGB565,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGBX8888,
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DRM_FORMAT_BGRX8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_RGBA8888,
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DRM_FORMAT_BGRA8888,
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};
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static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
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DRM_PLANE_TYPE_PRIMARY,
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DRM_PLANE_TYPE_CURSOR,
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};
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static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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if (ctx->suspended)
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return;
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atomic_set(&ctx->wait_vsync_event, 1);
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/*
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* wait for DECON to signal VSYNC interrupt or return after
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* timeout which is set to 50ms (refresh rate of 20).
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*/
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if (!wait_event_timeout(ctx->wait_vsync_queue,
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!atomic_read(&ctx->wait_vsync_event),
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HZ/20))
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DRM_DEBUG_KMS("vblank wait timed out.\n");
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}
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static void decon_clear_channels(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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unsigned int win, ch_enabled = 0;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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/* Check if any channel is enabled. */
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for (win = 0; win < WINDOWS_NR; win++) {
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u32 val = readl(ctx->regs + WINCON(win));
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if (val & WINCONx_ENWIN) {
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val &= ~WINCONx_ENWIN;
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writel(val, ctx->regs + WINCON(win));
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ch_enabled = 1;
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}
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}
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/* Wait for vsync, as disable channel takes effect at next vsync */
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if (ch_enabled)
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decon_wait_for_vblank(ctx->crtc);
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}
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static int decon_ctx_initialize(struct decon_context *ctx,
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struct drm_device *drm_dev)
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{
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struct exynos_drm_private *priv = drm_dev->dev_private;
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int ret;
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ctx->drm_dev = drm_dev;
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ctx->pipe = priv->pipe++;
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decon_clear_channels(ctx->crtc);
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ret = drm_iommu_attach_device(drm_dev, ctx->dev);
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if (ret)
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priv->pipe--;
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return ret;
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}
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static void decon_ctx_remove(struct decon_context *ctx)
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{
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/* detach this sub driver from iommu mapping if supported. */
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drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
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}
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static u32 decon_calc_clkdiv(struct decon_context *ctx,
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const struct drm_display_mode *mode)
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{
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unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
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u32 clkdiv;
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/* Find the clock divider value that gets us closest to ideal_clk */
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clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
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return (clkdiv < 0x100) ? clkdiv : 0xff;
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}
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static void decon_commit(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
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u32 val, clkdiv;
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if (ctx->suspended)
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return;
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/* nothing to do if we haven't set the mode yet */
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if (mode->htotal == 0 || mode->vtotal == 0)
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return;
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if (!ctx->i80_if) {
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int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
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/* setup vertical timing values. */
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vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
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vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
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vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
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val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
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writel(val, ctx->regs + VIDTCON0);
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val = VIDTCON1_VSPW(vsync_len - 1);
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writel(val, ctx->regs + VIDTCON1);
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/* setup horizontal timing values. */
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hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
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hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
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hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
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/* setup horizontal timing values. */
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val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
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writel(val, ctx->regs + VIDTCON2);
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val = VIDTCON3_HSPW(hsync_len - 1);
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writel(val, ctx->regs + VIDTCON3);
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}
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/* setup horizontal and vertical display size. */
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val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
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VIDTCON4_HOZVAL(mode->hdisplay - 1);
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writel(val, ctx->regs + VIDTCON4);
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writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
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/*
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* fields of register with prefix '_F' would be updated
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* at vsync(same as dma start)
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*/
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val = VIDCON0_ENVID | VIDCON0_ENVID_F;
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writel(val, ctx->regs + VIDCON0);
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clkdiv = decon_calc_clkdiv(ctx, mode);
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if (clkdiv > 1) {
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val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
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writel(val, ctx->regs + VCLKCON1);
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writel(val, ctx->regs + VCLKCON2);
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}
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val = readl(ctx->regs + DECON_UPDATE);
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val |= DECON_UPDATE_STANDALONE_F;
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writel(val, ctx->regs + DECON_UPDATE);
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}
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static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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u32 val;
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if (ctx->suspended)
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return -EPERM;
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if (!test_and_set_bit(0, &ctx->irq_flags)) {
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val = readl(ctx->regs + VIDINTCON0);
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val |= VIDINTCON0_INT_ENABLE;
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if (!ctx->i80_if) {
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val |= VIDINTCON0_INT_FRAME;
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val &= ~VIDINTCON0_FRAMESEL0_MASK;
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val |= VIDINTCON0_FRAMESEL0_VSYNC;
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}
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writel(val, ctx->regs + VIDINTCON0);
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}
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return 0;
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}
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static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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u32 val;
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if (ctx->suspended)
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return;
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if (test_and_clear_bit(0, &ctx->irq_flags)) {
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val = readl(ctx->regs + VIDINTCON0);
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val &= ~VIDINTCON0_INT_ENABLE;
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if (!ctx->i80_if)
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val &= ~VIDINTCON0_INT_FRAME;
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writel(val, ctx->regs + VIDINTCON0);
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}
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}
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static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
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struct drm_framebuffer *fb)
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{
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unsigned long val;
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int padding;
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val = readl(ctx->regs + WINCON(win));
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val &= ~WINCONx_BPPMODE_MASK;
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switch (fb->pixel_format) {
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case DRM_FORMAT_RGB565:
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val |= WINCONx_BPPMODE_16BPP_565;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_XRGB8888:
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val |= WINCONx_BPPMODE_24BPP_xRGB;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_XBGR8888:
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val |= WINCONx_BPPMODE_24BPP_xBGR;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_RGBX8888:
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val |= WINCONx_BPPMODE_24BPP_RGBx;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_BGRX8888:
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val |= WINCONx_BPPMODE_24BPP_BGRx;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_ARGB8888:
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val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
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WINCONx_ALPHA_SEL;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_ABGR8888:
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val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
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WINCONx_ALPHA_SEL;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_RGBA8888:
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val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
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WINCONx_ALPHA_SEL;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case DRM_FORMAT_BGRA8888:
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val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
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WINCONx_ALPHA_SEL;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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default:
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DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
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val |= WINCONx_BPPMODE_24BPP_xRGB;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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}
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DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel);
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/*
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* In case of exynos, setting dma-burst to 16Word causes permanent
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* tearing for very small buffers, e.g. cursor buffer. Burst Mode
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* switching which is based on plane size is not recommended as
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* plane size varies a lot towards the end of the screen and rapid
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* movement causes unstable DMA which results into iommu crash/tear.
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*/
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padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width;
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if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
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val &= ~WINCONx_BURSTLEN_MASK;
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val |= WINCONx_BURSTLEN_8WORD;
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}
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writel(val, ctx->regs + WINCON(win));
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}
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static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
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{
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unsigned int keycon0 = 0, keycon1 = 0;
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keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
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WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
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keycon1 = WxKEYCON1_COLVAL(0xffffffff);
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writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
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writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
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}
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/**
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* shadow_protect_win() - disable updating values from shadow registers at vsync
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*
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* @win: window to protect registers for
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* @protect: 1 to protect (disable updates)
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*/
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static void decon_shadow_protect_win(struct decon_context *ctx,
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unsigned int win, bool protect)
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{
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u32 bits, val;
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bits = SHADOWCON_WINx_PROTECT(win);
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val = readl(ctx->regs + SHADOWCON);
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if (protect)
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val |= bits;
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else
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val &= ~bits;
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writel(val, ctx->regs + SHADOWCON);
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}
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static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
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{
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struct decon_context *ctx = crtc->ctx;
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int i;
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if (ctx->suspended)
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return;
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for (i = 0; i < WINDOWS_NR; i++)
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decon_shadow_protect_win(ctx, i, true);
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}
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static void decon_update_plane(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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struct exynos_drm_plane_state *state =
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to_exynos_plane_state(plane->base.state);
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struct decon_context *ctx = crtc->ctx;
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struct drm_framebuffer *fb = state->base.fb;
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int padding;
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unsigned long val, alpha;
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unsigned int last_x;
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unsigned int last_y;
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unsigned int win = plane->index;
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unsigned int bpp = fb->bits_per_pixel >> 3;
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unsigned int pitch = fb->pitches[0];
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if (ctx->suspended)
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return;
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/*
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* SHADOWCON/PRTCON register is used for enabling timing.
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*
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* for example, once only width value of a register is set,
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* if the dma is started then decon hardware could malfunction so
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* with protect window setting, the register fields with prefix '_F'
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* wouldn't be updated at vsync also but updated once unprotect window
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* is set.
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*/
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/* buffer start address */
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val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
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writel(val, ctx->regs + VIDW_BUF_START(win));
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padding = (pitch / bpp) - fb->width;
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/* buffer size */
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writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
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writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
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/* offset from the start of the buffer to read */
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writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
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writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
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DRM_DEBUG_KMS("start addr = 0x%lx\n",
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(unsigned long)val);
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DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
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state->crtc.w, state->crtc.h);
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val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
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VIDOSDxA_TOPLEFT_Y(state->crtc.y);
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writel(val, ctx->regs + VIDOSD_A(win));
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last_x = state->crtc.x + state->crtc.w;
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if (last_x)
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last_x--;
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last_y = state->crtc.y + state->crtc.h;
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if (last_y)
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last_y--;
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val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
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writel(val, ctx->regs + VIDOSD_B(win));
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DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
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state->crtc.x, state->crtc.y, last_x, last_y);
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/* OSD alpha */
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alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
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VIDOSDxC_ALPHA0_G_F(0x0) |
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VIDOSDxC_ALPHA0_B_F(0x0);
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writel(alpha, ctx->regs + VIDOSD_C(win));
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alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
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VIDOSDxD_ALPHA1_G_F(0xff) |
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VIDOSDxD_ALPHA1_B_F(0xff);
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writel(alpha, ctx->regs + VIDOSD_D(win));
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decon_win_set_pixfmt(ctx, win, fb);
|
|
|
|
/* hardware window 0 doesn't support color key. */
|
|
if (win != 0)
|
|
decon_win_set_colkey(ctx, win);
|
|
|
|
/* wincon */
|
|
val = readl(ctx->regs + WINCON(win));
|
|
val |= WINCONx_TRIPLE_BUF_MODE;
|
|
val |= WINCONx_ENWIN;
|
|
writel(val, ctx->regs + WINCON(win));
|
|
|
|
/* Enable DMA channel and unprotect windows */
|
|
decon_shadow_protect_win(ctx, win, false);
|
|
|
|
val = readl(ctx->regs + DECON_UPDATE);
|
|
val |= DECON_UPDATE_STANDALONE_F;
|
|
writel(val, ctx->regs + DECON_UPDATE);
|
|
}
|
|
|
|
static void decon_disable_plane(struct exynos_drm_crtc *crtc,
|
|
struct exynos_drm_plane *plane)
|
|
{
|
|
struct decon_context *ctx = crtc->ctx;
|
|
unsigned int win = plane->index;
|
|
u32 val;
|
|
|
|
if (ctx->suspended)
|
|
return;
|
|
|
|
/* protect windows */
|
|
decon_shadow_protect_win(ctx, win, true);
|
|
|
|
/* wincon */
|
|
val = readl(ctx->regs + WINCON(win));
|
|
val &= ~WINCONx_ENWIN;
|
|
writel(val, ctx->regs + WINCON(win));
|
|
|
|
val = readl(ctx->regs + DECON_UPDATE);
|
|
val |= DECON_UPDATE_STANDALONE_F;
|
|
writel(val, ctx->regs + DECON_UPDATE);
|
|
}
|
|
|
|
static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
|
|
{
|
|
struct decon_context *ctx = crtc->ctx;
|
|
int i;
|
|
|
|
if (ctx->suspended)
|
|
return;
|
|
|
|
for (i = 0; i < WINDOWS_NR; i++)
|
|
decon_shadow_protect_win(ctx, i, false);
|
|
}
|
|
|
|
static void decon_init(struct decon_context *ctx)
|
|
{
|
|
u32 val;
|
|
|
|
writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
|
|
|
|
val = VIDOUTCON0_DISP_IF_0_ON;
|
|
if (!ctx->i80_if)
|
|
val |= VIDOUTCON0_RGBIF;
|
|
writel(val, ctx->regs + VIDOUTCON0);
|
|
|
|
writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
|
|
|
|
if (!ctx->i80_if)
|
|
writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
|
|
}
|
|
|
|
static void decon_enable(struct exynos_drm_crtc *crtc)
|
|
{
|
|
struct decon_context *ctx = crtc->ctx;
|
|
|
|
if (!ctx->suspended)
|
|
return;
|
|
|
|
pm_runtime_get_sync(ctx->dev);
|
|
|
|
decon_init(ctx);
|
|
|
|
/* if vblank was enabled status, enable it again. */
|
|
if (test_and_clear_bit(0, &ctx->irq_flags))
|
|
decon_enable_vblank(ctx->crtc);
|
|
|
|
decon_commit(ctx->crtc);
|
|
|
|
ctx->suspended = false;
|
|
}
|
|
|
|
static void decon_disable(struct exynos_drm_crtc *crtc)
|
|
{
|
|
struct decon_context *ctx = crtc->ctx;
|
|
int i;
|
|
|
|
if (ctx->suspended)
|
|
return;
|
|
|
|
/*
|
|
* We need to make sure that all windows are disabled before we
|
|
* suspend that connector. Otherwise we might try to scan from
|
|
* a destroyed buffer later.
|
|
*/
|
|
for (i = 0; i < WINDOWS_NR; i++)
|
|
decon_disable_plane(crtc, &ctx->planes[i]);
|
|
|
|
pm_runtime_put_sync(ctx->dev);
|
|
|
|
ctx->suspended = true;
|
|
}
|
|
|
|
static const struct exynos_drm_crtc_ops decon_crtc_ops = {
|
|
.enable = decon_enable,
|
|
.disable = decon_disable,
|
|
.commit = decon_commit,
|
|
.enable_vblank = decon_enable_vblank,
|
|
.disable_vblank = decon_disable_vblank,
|
|
.wait_for_vblank = decon_wait_for_vblank,
|
|
.atomic_begin = decon_atomic_begin,
|
|
.update_plane = decon_update_plane,
|
|
.disable_plane = decon_disable_plane,
|
|
.atomic_flush = decon_atomic_flush,
|
|
};
|
|
|
|
|
|
static irqreturn_t decon_irq_handler(int irq, void *dev_id)
|
|
{
|
|
struct decon_context *ctx = (struct decon_context *)dev_id;
|
|
u32 val, clear_bit;
|
|
int win;
|
|
|
|
val = readl(ctx->regs + VIDINTCON1);
|
|
|
|
clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
|
|
if (val & clear_bit)
|
|
writel(clear_bit, ctx->regs + VIDINTCON1);
|
|
|
|
/* check the crtc is detached already from encoder */
|
|
if (ctx->pipe < 0 || !ctx->drm_dev)
|
|
goto out;
|
|
|
|
if (!ctx->i80_if) {
|
|
drm_crtc_handle_vblank(&ctx->crtc->base);
|
|
for (win = 0 ; win < WINDOWS_NR ; win++) {
|
|
struct exynos_drm_plane *plane = &ctx->planes[win];
|
|
|
|
if (!plane->pending_fb)
|
|
continue;
|
|
|
|
exynos_drm_crtc_finish_update(ctx->crtc, plane);
|
|
}
|
|
|
|
/* set wait vsync event to zero and wake up queue. */
|
|
if (atomic_read(&ctx->wait_vsync_event)) {
|
|
atomic_set(&ctx->wait_vsync_event, 0);
|
|
wake_up(&ctx->wait_vsync_queue);
|
|
}
|
|
}
|
|
out:
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int decon_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct decon_context *ctx = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = data;
|
|
struct exynos_drm_plane *exynos_plane;
|
|
unsigned int i;
|
|
int ret;
|
|
|
|
ret = decon_ctx_initialize(ctx, drm_dev);
|
|
if (ret) {
|
|
DRM_ERROR("decon_ctx_initialize failed.\n");
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < WINDOWS_NR; i++) {
|
|
ctx->configs[i].pixel_formats = decon_formats;
|
|
ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
|
|
ctx->configs[i].zpos = i;
|
|
ctx->configs[i].type = decon_win_types[i];
|
|
|
|
ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
|
|
1 << ctx->pipe, &ctx->configs[i]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
exynos_plane = &ctx->planes[DEFAULT_WIN];
|
|
ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
|
|
ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
|
|
&decon_crtc_ops, ctx);
|
|
if (IS_ERR(ctx->crtc)) {
|
|
decon_ctx_remove(ctx);
|
|
return PTR_ERR(ctx->crtc);
|
|
}
|
|
|
|
if (ctx->encoder)
|
|
exynos_dpi_bind(drm_dev, ctx->encoder);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static void decon_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct decon_context *ctx = dev_get_drvdata(dev);
|
|
|
|
decon_disable(ctx->crtc);
|
|
|
|
if (ctx->encoder)
|
|
exynos_dpi_remove(ctx->encoder);
|
|
|
|
decon_ctx_remove(ctx);
|
|
}
|
|
|
|
static const struct component_ops decon_component_ops = {
|
|
.bind = decon_bind,
|
|
.unbind = decon_unbind,
|
|
};
|
|
|
|
static int decon_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct decon_context *ctx;
|
|
struct device_node *i80_if_timings;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
if (!dev->of_node)
|
|
return -ENODEV;
|
|
|
|
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
|
if (!ctx)
|
|
return -ENOMEM;
|
|
|
|
ctx->dev = dev;
|
|
ctx->suspended = true;
|
|
|
|
i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
|
|
if (i80_if_timings)
|
|
ctx->i80_if = true;
|
|
of_node_put(i80_if_timings);
|
|
|
|
ctx->regs = of_iomap(dev->of_node, 0);
|
|
if (!ctx->regs)
|
|
return -ENOMEM;
|
|
|
|
ctx->pclk = devm_clk_get(dev, "pclk_decon0");
|
|
if (IS_ERR(ctx->pclk)) {
|
|
dev_err(dev, "failed to get bus clock pclk\n");
|
|
ret = PTR_ERR(ctx->pclk);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
ctx->aclk = devm_clk_get(dev, "aclk_decon0");
|
|
if (IS_ERR(ctx->aclk)) {
|
|
dev_err(dev, "failed to get bus clock aclk\n");
|
|
ret = PTR_ERR(ctx->aclk);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
ctx->eclk = devm_clk_get(dev, "decon0_eclk");
|
|
if (IS_ERR(ctx->eclk)) {
|
|
dev_err(dev, "failed to get eclock\n");
|
|
ret = PTR_ERR(ctx->eclk);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
ctx->vclk = devm_clk_get(dev, "decon0_vclk");
|
|
if (IS_ERR(ctx->vclk)) {
|
|
dev_err(dev, "failed to get vclock\n");
|
|
ret = PTR_ERR(ctx->vclk);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
|
|
ctx->i80_if ? "lcd_sys" : "vsync");
|
|
if (!res) {
|
|
dev_err(dev, "irq request failed.\n");
|
|
ret = -ENXIO;
|
|
goto err_iounmap;
|
|
}
|
|
|
|
ret = devm_request_irq(dev, res->start, decon_irq_handler,
|
|
0, "drm_decon", ctx);
|
|
if (ret) {
|
|
dev_err(dev, "irq request failed.\n");
|
|
goto err_iounmap;
|
|
}
|
|
|
|
init_waitqueue_head(&ctx->wait_vsync_queue);
|
|
atomic_set(&ctx->wait_vsync_event, 0);
|
|
|
|
platform_set_drvdata(pdev, ctx);
|
|
|
|
ctx->encoder = exynos_dpi_probe(dev);
|
|
if (IS_ERR(ctx->encoder)) {
|
|
ret = PTR_ERR(ctx->encoder);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
ret = component_add(dev, &decon_component_ops);
|
|
if (ret)
|
|
goto err_disable_pm_runtime;
|
|
|
|
return ret;
|
|
|
|
err_disable_pm_runtime:
|
|
pm_runtime_disable(dev);
|
|
|
|
err_iounmap:
|
|
iounmap(ctx->regs);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int decon_remove(struct platform_device *pdev)
|
|
{
|
|
struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
iounmap(ctx->regs);
|
|
|
|
component_del(&pdev->dev, &decon_component_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int exynos7_decon_suspend(struct device *dev)
|
|
{
|
|
struct decon_context *ctx = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(ctx->vclk);
|
|
clk_disable_unprepare(ctx->eclk);
|
|
clk_disable_unprepare(ctx->aclk);
|
|
clk_disable_unprepare(ctx->pclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos7_decon_resume(struct device *dev)
|
|
{
|
|
struct decon_context *ctx = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(ctx->pclk);
|
|
if (ret < 0) {
|
|
DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(ctx->aclk);
|
|
if (ret < 0) {
|
|
DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(ctx->eclk);
|
|
if (ret < 0) {
|
|
DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(ctx->vclk);
|
|
if (ret < 0) {
|
|
DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops exynos7_decon_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
|
|
NULL)
|
|
};
|
|
|
|
struct platform_driver decon_driver = {
|
|
.probe = decon_probe,
|
|
.remove = decon_remove,
|
|
.driver = {
|
|
.name = "exynos-decon",
|
|
.pm = &exynos7_decon_pm_ops,
|
|
.of_match_table = decon_driver_dt_match,
|
|
},
|
|
};
|