![Thierry Reding](/assets/img/avatar_default.png)
The GMA500 driver redefines many constants already found in the generic header. Replace uses of the custom defines by the standard ones and get rid of the duplicate defininitions. Acked-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
676 lines
16 KiB
C
676 lines
16 KiB
C
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jackie Li<yaodong.li@intel.com>
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*/
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#include <linux/freezer.h>
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#include <video/mipi_display.h>
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#include "mdfld_dsi_output.h"
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#include "mdfld_dsi_pkg_sender.h"
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#include "mdfld_dsi_dpi.h"
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#define MDFLD_DSI_READ_MAX_COUNT 5000
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enum {
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MDFLD_DSI_PANEL_MODE_SLEEP = 0x1,
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};
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enum {
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MDFLD_DSI_PKG_SENDER_FREE = 0x0,
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MDFLD_DSI_PKG_SENDER_BUSY = 0x1,
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};
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static const char *const dsi_errors[] = {
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"RX SOT Error",
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"RX SOT Sync Error",
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"RX EOT Sync Error",
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"RX Escape Mode Entry Error",
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"RX LP TX Sync Error",
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"RX HS Receive Timeout Error",
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"RX False Control Error",
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"RX ECC Single Bit Error",
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"RX ECC Multibit Error",
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"RX Checksum Error",
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"RX DSI Data Type Not Recognised",
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"RX DSI VC ID Invalid",
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"TX False Control Error",
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"TX ECC Single Bit Error",
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"TX ECC Multibit Error",
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"TX Checksum Error",
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"TX DSI Data Type Not Recognised",
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"TX DSI VC ID invalid",
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"High Contention",
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"Low contention",
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"DPI FIFO Under run",
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"HS TX Timeout",
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"LP RX Timeout",
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"Turn Around ACK Timeout",
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"ACK With No Error",
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"RX Invalid TX Length",
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"RX Prot Violation",
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"HS Generic Write FIFO Full",
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"LP Generic Write FIFO Full",
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"Generic Read Data Avail"
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"Special Packet Sent",
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"Tearing Effect",
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};
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static inline int wait_for_gen_fifo_empty(struct mdfld_dsi_pkg_sender *sender,
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u32 mask)
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{
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struct drm_device *dev = sender->dev;
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u32 gen_fifo_stat_reg = sender->mipi_gen_fifo_stat_reg;
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int retry = 0xffff;
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while (retry--) {
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if ((mask & REG_READ(gen_fifo_stat_reg)) == mask)
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return 0;
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udelay(100);
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}
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DRM_ERROR("fifo is NOT empty 0x%08x\n", REG_READ(gen_fifo_stat_reg));
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return -EIO;
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}
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static int wait_for_all_fifos_empty(struct mdfld_dsi_pkg_sender *sender)
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{
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return wait_for_gen_fifo_empty(sender, (BIT(2) | BIT(10) | BIT(18) |
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BIT(26) | BIT(27) | BIT(28)));
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}
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static int wait_for_lp_fifos_empty(struct mdfld_dsi_pkg_sender *sender)
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{
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return wait_for_gen_fifo_empty(sender, (BIT(10) | BIT(26)));
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}
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static int wait_for_hs_fifos_empty(struct mdfld_dsi_pkg_sender *sender)
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{
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return wait_for_gen_fifo_empty(sender, (BIT(2) | BIT(18)));
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}
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static int handle_dsi_error(struct mdfld_dsi_pkg_sender *sender, u32 mask)
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{
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u32 intr_stat_reg = sender->mipi_intr_stat_reg;
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struct drm_device *dev = sender->dev;
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dev_dbg(sender->dev->dev, "Handling error 0x%08x\n", mask);
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switch (mask) {
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case BIT(0):
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case BIT(1):
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case BIT(2):
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case BIT(3):
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case BIT(4):
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case BIT(5):
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case BIT(6):
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case BIT(7):
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case BIT(8):
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case BIT(9):
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case BIT(10):
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case BIT(11):
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case BIT(12):
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case BIT(13):
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dev_dbg(sender->dev->dev, "No Action required\n");
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break;
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case BIT(14):
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/*wait for all fifo empty*/
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/*wait_for_all_fifos_empty(sender)*/
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break;
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case BIT(15):
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dev_dbg(sender->dev->dev, "No Action required\n");
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break;
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case BIT(16):
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break;
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case BIT(17):
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break;
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case BIT(18):
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case BIT(19):
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dev_dbg(sender->dev->dev, "High/Low contention detected\n");
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/*wait for contention recovery time*/
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/*mdelay(10);*/
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/*wait for all fifo empty*/
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if (0)
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wait_for_all_fifos_empty(sender);
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break;
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case BIT(20):
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dev_dbg(sender->dev->dev, "No Action required\n");
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break;
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case BIT(21):
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/*wait for all fifo empty*/
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/*wait_for_all_fifos_empty(sender);*/
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break;
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case BIT(22):
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break;
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case BIT(23):
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case BIT(24):
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case BIT(25):
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case BIT(26):
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case BIT(27):
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dev_dbg(sender->dev->dev, "HS Gen fifo full\n");
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REG_WRITE(intr_stat_reg, mask);
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wait_for_hs_fifos_empty(sender);
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break;
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case BIT(28):
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dev_dbg(sender->dev->dev, "LP Gen fifo full\n");
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REG_WRITE(intr_stat_reg, mask);
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wait_for_lp_fifos_empty(sender);
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break;
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case BIT(29):
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case BIT(30):
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case BIT(31):
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dev_dbg(sender->dev->dev, "No Action required\n");
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break;
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}
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if (mask & REG_READ(intr_stat_reg))
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dev_dbg(sender->dev->dev,
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"Cannot clean interrupt 0x%08x\n", mask);
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return 0;
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}
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static int dsi_error_handler(struct mdfld_dsi_pkg_sender *sender)
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{
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struct drm_device *dev = sender->dev;
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u32 intr_stat_reg = sender->mipi_intr_stat_reg;
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u32 mask;
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u32 intr_stat;
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int i;
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int err = 0;
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intr_stat = REG_READ(intr_stat_reg);
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for (i = 0; i < 32; i++) {
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mask = (0x00000001UL) << i;
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if (intr_stat & mask) {
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dev_dbg(sender->dev->dev, "[DSI]: %s\n", dsi_errors[i]);
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err = handle_dsi_error(sender, mask);
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if (err)
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DRM_ERROR("Cannot handle error\n");
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}
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}
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return err;
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}
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static int send_short_pkg(struct mdfld_dsi_pkg_sender *sender, u8 data_type,
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u8 cmd, u8 param, bool hs)
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{
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struct drm_device *dev = sender->dev;
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u32 ctrl_reg;
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u32 val;
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u8 virtual_channel = 0;
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if (hs) {
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ctrl_reg = sender->mipi_hs_gen_ctrl_reg;
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/* FIXME: wait_for_hs_fifos_empty(sender); */
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} else {
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ctrl_reg = sender->mipi_lp_gen_ctrl_reg;
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/* FIXME: wait_for_lp_fifos_empty(sender); */
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}
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val = FLD_VAL(param, 23, 16) | FLD_VAL(cmd, 15, 8) |
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FLD_VAL(virtual_channel, 7, 6) | FLD_VAL(data_type, 5, 0);
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REG_WRITE(ctrl_reg, val);
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return 0;
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}
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static int send_long_pkg(struct mdfld_dsi_pkg_sender *sender, u8 data_type,
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u8 *data, int len, bool hs)
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{
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struct drm_device *dev = sender->dev;
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u32 ctrl_reg;
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u32 data_reg;
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u32 val;
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u8 *p;
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u8 b1, b2, b3, b4;
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u8 virtual_channel = 0;
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int i;
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if (hs) {
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ctrl_reg = sender->mipi_hs_gen_ctrl_reg;
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data_reg = sender->mipi_hs_gen_data_reg;
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/* FIXME: wait_for_hs_fifos_empty(sender); */
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} else {
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ctrl_reg = sender->mipi_lp_gen_ctrl_reg;
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data_reg = sender->mipi_lp_gen_data_reg;
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/* FIXME: wait_for_lp_fifos_empty(sender); */
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}
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p = data;
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for (i = 0; i < len / 4; i++) {
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b1 = *p++;
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b2 = *p++;
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b3 = *p++;
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b4 = *p++;
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REG_WRITE(data_reg, b4 << 24 | b3 << 16 | b2 << 8 | b1);
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}
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i = len % 4;
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if (i) {
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b1 = 0; b2 = 0; b3 = 0;
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switch (i) {
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case 3:
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b1 = *p++;
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b2 = *p++;
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b3 = *p++;
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break;
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case 2:
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b1 = *p++;
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b2 = *p++;
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break;
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case 1:
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b1 = *p++;
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break;
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}
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REG_WRITE(data_reg, b3 << 16 | b2 << 8 | b1);
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}
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val = FLD_VAL(len, 23, 8) | FLD_VAL(virtual_channel, 7, 6) |
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FLD_VAL(data_type, 5, 0);
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REG_WRITE(ctrl_reg, val);
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return 0;
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}
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static int send_pkg_prepare(struct mdfld_dsi_pkg_sender *sender, u8 data_type,
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u8 *data, u16 len)
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{
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u8 cmd;
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switch (data_type) {
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case MIPI_DSI_DCS_SHORT_WRITE:
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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case MIPI_DSI_DCS_LONG_WRITE:
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cmd = *data;
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break;
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default:
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return 0;
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}
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/*this prevents other package sending while doing msleep*/
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sender->status = MDFLD_DSI_PKG_SENDER_BUSY;
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/*wait for 120 milliseconds in case exit_sleep_mode just be sent*/
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if (unlikely(cmd == MIPI_DCS_ENTER_SLEEP_MODE)) {
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/*TODO: replace it with msleep later*/
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mdelay(120);
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}
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if (unlikely(cmd == MIPI_DCS_EXIT_SLEEP_MODE)) {
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/*TODO: replace it with msleep later*/
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mdelay(120);
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}
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return 0;
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}
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static int send_pkg_done(struct mdfld_dsi_pkg_sender *sender, u8 data_type,
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u8 *data, u16 len)
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{
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u8 cmd;
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switch (data_type) {
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case MIPI_DSI_DCS_SHORT_WRITE:
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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case MIPI_DSI_DCS_LONG_WRITE:
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cmd = *data;
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break;
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default:
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return 0;
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}
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/*update panel status*/
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if (unlikely(cmd == MIPI_DCS_ENTER_SLEEP_MODE)) {
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sender->panel_mode |= MDFLD_DSI_PANEL_MODE_SLEEP;
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/*TODO: replace it with msleep later*/
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mdelay(120);
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} else if (unlikely(cmd == MIPI_DCS_EXIT_SLEEP_MODE)) {
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sender->panel_mode &= ~MDFLD_DSI_PANEL_MODE_SLEEP;
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/*TODO: replace it with msleep later*/
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mdelay(120);
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} else if (unlikely(cmd == MIPI_DCS_SOFT_RESET)) {
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/*TODO: replace it with msleep later*/
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mdelay(5);
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}
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sender->status = MDFLD_DSI_PKG_SENDER_FREE;
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return 0;
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}
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static int send_pkg(struct mdfld_dsi_pkg_sender *sender, u8 data_type,
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u8 *data, u16 len, bool hs)
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{
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int ret;
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/*handle DSI error*/
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ret = dsi_error_handler(sender);
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if (ret) {
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DRM_ERROR("Error handling failed\n");
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return -EAGAIN;
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}
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/* send pkg */
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if (sender->status == MDFLD_DSI_PKG_SENDER_BUSY) {
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DRM_ERROR("sender is busy\n");
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return -EAGAIN;
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}
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ret = send_pkg_prepare(sender, data_type, data, len);
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if (ret) {
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DRM_ERROR("send_pkg_prepare error\n");
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return ret;
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}
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switch (data_type) {
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case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
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case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
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case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
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case MIPI_DSI_DCS_SHORT_WRITE:
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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case MIPI_DSI_DCS_READ:
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ret = send_short_pkg(sender, data_type, data[0], data[1], hs);
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break;
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case MIPI_DSI_GENERIC_LONG_WRITE:
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case MIPI_DSI_DCS_LONG_WRITE:
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ret = send_long_pkg(sender, data_type, data, len, hs);
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break;
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}
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send_pkg_done(sender, data_type, data, len);
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/*FIXME: should I query complete and fifo empty here?*/
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return ret;
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}
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int mdfld_dsi_send_mcs_long(struct mdfld_dsi_pkg_sender *sender, u8 *data,
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u32 len, bool hs)
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{
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unsigned long flags;
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if (!sender || !data || !len) {
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DRM_ERROR("Invalid parameters\n");
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return -EINVAL;
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}
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spin_lock_irqsave(&sender->lock, flags);
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send_pkg(sender, MIPI_DSI_DCS_LONG_WRITE, data, len, hs);
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spin_unlock_irqrestore(&sender->lock, flags);
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return 0;
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}
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int mdfld_dsi_send_mcs_short(struct mdfld_dsi_pkg_sender *sender, u8 cmd,
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u8 param, u8 param_num, bool hs)
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{
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u8 data[2];
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unsigned long flags;
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u8 data_type;
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if (!sender) {
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DRM_ERROR("Invalid parameter\n");
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return -EINVAL;
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}
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data[0] = cmd;
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if (param_num) {
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data_type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
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data[1] = param;
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} else {
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data_type = MIPI_DSI_DCS_SHORT_WRITE;
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data[1] = 0;
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}
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spin_lock_irqsave(&sender->lock, flags);
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send_pkg(sender, data_type, data, sizeof(data), hs);
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spin_unlock_irqrestore(&sender->lock, flags);
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return 0;
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}
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int mdfld_dsi_send_gen_short(struct mdfld_dsi_pkg_sender *sender, u8 param0,
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u8 param1, u8 param_num, bool hs)
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{
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u8 data[2];
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unsigned long flags;
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u8 data_type;
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if (!sender || param_num > 2) {
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DRM_ERROR("Invalid parameter\n");
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return -EINVAL;
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}
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switch (param_num) {
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case 0:
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data_type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM;
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data[0] = 0;
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data[1] = 0;
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break;
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case 1:
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data_type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM;
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data[0] = param0;
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data[1] = 0;
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break;
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case 2:
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data_type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM;
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data[0] = param0;
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data[1] = param1;
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break;
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}
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spin_lock_irqsave(&sender->lock, flags);
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send_pkg(sender, data_type, data, sizeof(data), hs);
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spin_unlock_irqrestore(&sender->lock, flags);
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return 0;
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}
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int mdfld_dsi_send_gen_long(struct mdfld_dsi_pkg_sender *sender, u8 *data,
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u32 len, bool hs)
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{
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unsigned long flags;
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if (!sender || !data || !len) {
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DRM_ERROR("Invalid parameters\n");
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return -EINVAL;
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}
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spin_lock_irqsave(&sender->lock, flags);
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send_pkg(sender, MIPI_DSI_GENERIC_LONG_WRITE, data, len, hs);
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spin_unlock_irqrestore(&sender->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __read_panel_data(struct mdfld_dsi_pkg_sender *sender, u8 data_type,
|
|
u8 *data, u16 len, u32 *data_out, u16 len_out, bool hs)
|
|
{
|
|
unsigned long flags;
|
|
struct drm_device *dev = sender->dev;
|
|
int i;
|
|
u32 gen_data_reg;
|
|
int retry = MDFLD_DSI_READ_MAX_COUNT;
|
|
|
|
if (!sender || !data_out || !len_out) {
|
|
DRM_ERROR("Invalid parameters\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/**
|
|
* do reading.
|
|
* 0) send out generic read request
|
|
* 1) polling read data avail interrupt
|
|
* 2) read data
|
|
*/
|
|
spin_lock_irqsave(&sender->lock, flags);
|
|
|
|
REG_WRITE(sender->mipi_intr_stat_reg, BIT(29));
|
|
|
|
if ((REG_READ(sender->mipi_intr_stat_reg) & BIT(29)))
|
|
DRM_ERROR("Can NOT clean read data valid interrupt\n");
|
|
|
|
/*send out read request*/
|
|
send_pkg(sender, data_type, data, len, hs);
|
|
|
|
/*polling read data avail interrupt*/
|
|
while (retry && !(REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) {
|
|
udelay(100);
|
|
retry--;
|
|
}
|
|
|
|
if (!retry) {
|
|
spin_unlock_irqrestore(&sender->lock, flags);
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
REG_WRITE(sender->mipi_intr_stat_reg, BIT(29));
|
|
|
|
/*read data*/
|
|
if (hs)
|
|
gen_data_reg = sender->mipi_hs_gen_data_reg;
|
|
else
|
|
gen_data_reg = sender->mipi_lp_gen_data_reg;
|
|
|
|
for (i = 0; i < len_out; i++)
|
|
*(data_out + i) = REG_READ(gen_data_reg);
|
|
|
|
spin_unlock_irqrestore(&sender->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mdfld_dsi_read_mcs(struct mdfld_dsi_pkg_sender *sender, u8 cmd,
|
|
u32 *data, u16 len, bool hs)
|
|
{
|
|
if (!sender || !data || !len) {
|
|
DRM_ERROR("Invalid parameters\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return __read_panel_data(sender, MIPI_DSI_DCS_READ, &cmd, 1,
|
|
data, len, hs);
|
|
}
|
|
|
|
int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
|
|
int pipe)
|
|
{
|
|
struct mdfld_dsi_pkg_sender *pkg_sender;
|
|
struct mdfld_dsi_config *dsi_config =
|
|
mdfld_dsi_get_config(dsi_connector);
|
|
struct drm_device *dev = dsi_config->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
|
u32 mipi_val = 0;
|
|
|
|
if (!dsi_connector) {
|
|
DRM_ERROR("Invalid parameter\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pkg_sender = dsi_connector->pkg_sender;
|
|
|
|
if (!pkg_sender || IS_ERR(pkg_sender)) {
|
|
pkg_sender = kzalloc(sizeof(struct mdfld_dsi_pkg_sender),
|
|
GFP_KERNEL);
|
|
if (!pkg_sender) {
|
|
DRM_ERROR("Create DSI pkg sender failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
dsi_connector->pkg_sender = (void *)pkg_sender;
|
|
}
|
|
|
|
pkg_sender->dev = dev;
|
|
pkg_sender->dsi_connector = dsi_connector;
|
|
pkg_sender->pipe = pipe;
|
|
pkg_sender->pkg_num = 0;
|
|
pkg_sender->panel_mode = 0;
|
|
pkg_sender->status = MDFLD_DSI_PKG_SENDER_FREE;
|
|
|
|
/*init regs*/
|
|
/* FIXME: should just copy the regmap ptr ? */
|
|
pkg_sender->dpll_reg = map->dpll;
|
|
pkg_sender->dspcntr_reg = map->cntr;
|
|
pkg_sender->pipeconf_reg = map->conf;
|
|
pkg_sender->dsplinoff_reg = map->linoff;
|
|
pkg_sender->dspsurf_reg = map->surf;
|
|
pkg_sender->pipestat_reg = map->status;
|
|
|
|
pkg_sender->mipi_intr_stat_reg = MIPI_INTR_STAT_REG(pipe);
|
|
pkg_sender->mipi_lp_gen_data_reg = MIPI_LP_GEN_DATA_REG(pipe);
|
|
pkg_sender->mipi_hs_gen_data_reg = MIPI_HS_GEN_DATA_REG(pipe);
|
|
pkg_sender->mipi_lp_gen_ctrl_reg = MIPI_LP_GEN_CTRL_REG(pipe);
|
|
pkg_sender->mipi_hs_gen_ctrl_reg = MIPI_HS_GEN_CTRL_REG(pipe);
|
|
pkg_sender->mipi_gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe);
|
|
pkg_sender->mipi_data_addr_reg = MIPI_DATA_ADD_REG(pipe);
|
|
pkg_sender->mipi_data_len_reg = MIPI_DATA_LEN_REG(pipe);
|
|
pkg_sender->mipi_cmd_addr_reg = MIPI_CMD_ADD_REG(pipe);
|
|
pkg_sender->mipi_cmd_len_reg = MIPI_CMD_LEN_REG(pipe);
|
|
|
|
/*init lock*/
|
|
spin_lock_init(&pkg_sender->lock);
|
|
|
|
if (mdfld_get_panel_type(dev, pipe) != TC35876X) {
|
|
/**
|
|
* For video mode, don't enable DPI timing output here,
|
|
* will init the DPI timing output during mode setting.
|
|
*/
|
|
mipi_val = PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX;
|
|
|
|
if (pipe == 0)
|
|
mipi_val |= 0x2;
|
|
|
|
REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi_val);
|
|
REG_READ(MIPI_PORT_CONTROL(pipe));
|
|
|
|
/* do dsi controller init */
|
|
mdfld_dsi_controller_init(dsi_config, pipe);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mdfld_dsi_pkg_sender_destroy(struct mdfld_dsi_pkg_sender *sender)
|
|
{
|
|
if (!sender || IS_ERR(sender))
|
|
return;
|
|
|
|
/*free*/
|
|
kfree(sender);
|
|
}
|
|
|
|
|