![Vincent Abriou](/assets/img/avatar_default.png)
Better fit STI hardware structure. Planes are no more responsible of updating mixer information such as z-order and status. It is now up to the CRTC atomic flush to do it. Plane actions (enable or disable) are performed atomically. Disabling of a plane is synchronize with the vsync event. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
125 lines
3.4 KiB
C
125 lines
3.4 KiB
C
/*
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* Copyright (C) STMicroelectronics SA 2014
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* Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <drm/drmP.h>
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#include "sti_plane.h"
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#include "sti_vid.h"
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#include "sti_vtg.h"
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/* Registers */
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#define VID_CTL 0x00
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#define VID_ALP 0x04
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#define VID_CLF 0x08
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#define VID_VPO 0x0C
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#define VID_VPS 0x10
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#define VID_KEY1 0x28
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#define VID_KEY2 0x2C
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#define VID_MPR0 0x30
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#define VID_MPR1 0x34
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#define VID_MPR2 0x38
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#define VID_MPR3 0x3C
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#define VID_MST 0x68
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#define VID_BC 0x70
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#define VID_TINT 0x74
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#define VID_CSAT 0x78
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/* Registers values */
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#define VID_CTL_IGNORE (BIT(31) | BIT(30))
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#define VID_CTL_PSI_ENABLE (BIT(2) | BIT(1) | BIT(0))
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#define VID_ALP_OPAQUE 0x00000080
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#define VID_BC_DFLT 0x00008000
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#define VID_TINT_DFLT 0x00000000
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#define VID_CSAT_DFLT 0x00000080
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/* YCbCr to RGB BT709:
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* R = Y+1.5391Cr
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* G = Y-0.4590Cr-0.1826Cb
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* B = Y+1.8125Cb */
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#define VID_MPR0_BT709 0x0A800000
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#define VID_MPR1_BT709 0x0AC50000
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#define VID_MPR2_BT709 0x07150545
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#define VID_MPR3_BT709 0x00000AE8
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void sti_vid_commit(struct sti_vid *vid,
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struct drm_plane_state *state)
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{
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struct drm_crtc *crtc = state->crtc;
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struct drm_display_mode *mode = &crtc->mode;
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int dst_x = state->crtc_x;
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int dst_y = state->crtc_y;
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int dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x);
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int dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y);
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u32 val, ydo, xdo, yds, xds;
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/* Input / output size
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* Align to upper even value */
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dst_w = ALIGN(dst_w, 2);
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dst_h = ALIGN(dst_h, 2);
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/* Unmask */
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val = readl(vid->regs + VID_CTL);
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val &= ~VID_CTL_IGNORE;
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writel(val, vid->regs + VID_CTL);
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ydo = sti_vtg_get_line_number(*mode, dst_y);
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yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
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xdo = sti_vtg_get_pixel_number(*mode, dst_x);
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xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
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writel((ydo << 16) | xdo, vid->regs + VID_VPO);
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writel((yds << 16) | xds, vid->regs + VID_VPS);
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}
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void sti_vid_disable(struct sti_vid *vid)
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{
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u32 val;
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/* Mask */
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val = readl(vid->regs + VID_CTL);
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val |= VID_CTL_IGNORE;
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writel(val, vid->regs + VID_CTL);
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}
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static void sti_vid_init(struct sti_vid *vid)
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{
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/* Enable PSI, Mask layer */
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writel(VID_CTL_PSI_ENABLE | VID_CTL_IGNORE, vid->regs + VID_CTL);
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/* Opaque */
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writel(VID_ALP_OPAQUE, vid->regs + VID_ALP);
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/* Color conversion parameters */
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writel(VID_MPR0_BT709, vid->regs + VID_MPR0);
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writel(VID_MPR1_BT709, vid->regs + VID_MPR1);
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writel(VID_MPR2_BT709, vid->regs + VID_MPR2);
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writel(VID_MPR3_BT709, vid->regs + VID_MPR3);
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/* Brightness, contrast, tint, saturation */
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writel(VID_BC_DFLT, vid->regs + VID_BC);
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writel(VID_TINT_DFLT, vid->regs + VID_TINT);
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writel(VID_CSAT_DFLT, vid->regs + VID_CSAT);
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}
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struct sti_vid *sti_vid_create(struct device *dev, int id,
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void __iomem *baseaddr)
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{
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struct sti_vid *vid;
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vid = devm_kzalloc(dev, sizeof(*vid), GFP_KERNEL);
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if (!vid) {
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DRM_ERROR("Failed to allocate memory for VID\n");
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return NULL;
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}
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vid->dev = dev;
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vid->regs = baseaddr;
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vid->id = id;
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sti_vid_init(vid);
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return vid;
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}
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