![James Hogan](/assets/img/avatar_default.png)
Add source files from the Thread Binary Interface (TBI) library which provides useful low level operations and traps/context management. Among other things it handles interrupt/exception/syscall entry (in tbipcx.S). Signed-off-by: James Hogan <james.hogan@imgtec.com>
452 lines
16 KiB
ArmAsm
452 lines
16 KiB
ArmAsm
/*
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* tbipcx.S
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*
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* Copyright (C) 2001, 2002, 2007, 2009, 2012 Imagination Technologies.
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*
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* Asyncronous trigger handling including exceptions
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*/
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.file "tbipcx.S"
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#include <asm/metag_regs.h>
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#include <asm/tbx.h>
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/* BEGIN HACK */
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/* define these for now while doing inital conversion to GAS
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will fix properly later */
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/* Signal identifiers always have the TBID_SIGNAL_BIT set and contain the
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following related bit-fields */
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#define TBID_SIGNUM_S 2
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/* END HACK */
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#ifdef METAC_1_0
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/* Ax.4 is saved in TBICTX */
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#define A0_4 ,A0.4
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#else
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/* Ax.4 is NOT saved in TBICTX */
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#define A0_4
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#endif
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/* Size of the TBICTX structure */
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#define TBICTX_BYTES ((TBICTX_AX_REGS*8)+TBICTX_AX)
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#ifdef METAC_1_1
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#ifndef BOOTROM
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#ifndef SPECIAL_BUILD
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/* Jump straight into the boot ROM version of this code */
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#define CODE_USES_BOOTROM
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#endif
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#endif
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#endif
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/* Define space needed for CATCH buffer state in traditional units */
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#define CATCH_ENTRIES 5
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#define CATCH_ENTRY_BYTES 16
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#ifndef CODE_USES_BOOTROM
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#define A0GblIStP A0.15 /* PTBICTX for current thread in PRIV system */
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#define A1GblIGbP A1.15 /* Interrupt A1GbP value in PRIV system */
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#endif
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/*
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* TBIRES __TBIASyncTrigger( TBIRES State )
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*/
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.text
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.balign 4
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.global ___TBIASyncTrigger
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.type ___TBIASyncTrigger,function
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___TBIASyncTrigger:
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#ifdef CODE_USES_BOOTROM
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MOVT D0Re0,#HI(LINCORE_BASE)
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JUMP D0Re0,#0xA0
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#else
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MOV D0FrT,A0FrP /* Boing entry sequence */
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ADD A0FrP,A0StP,#0
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SETL [A0StP++],D0FrT,D1RtP
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MOV D0Re0,PCX /* Check for repeat call */
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MOVT D0FrT,#HI(___TBIBoingRTI+4)
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ADD D0FrT,D0FrT,#LO(___TBIBoingRTI+4)
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CMP D0Re0,D0FrT
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BEQ ___TBIBoingExit /* Already set up - come out */
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ADD D1Ar1,D1Ar1,#7 /* PRIV system stack here */
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MOV A0.2,A0StP /* else push context here */
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MOVS D0Re0,D0Ar2 /* Return in user mode? */
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ANDMB D1Ar1,D1Ar1,#0xfff8 /* align priv stack to 64-bit */
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MOV D1Re0,D1Ar1 /* and set result to arg */
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MOVMI A0.2,D1Ar1 /* use priv stack if PRIV set */
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/*
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* Generate an initial TBICTX to return to our own current call context
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*/
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MOVT D1Ar5,#HI(___TBIBoingExit) /* Go here to return */
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ADD D1Ar5,D1Ar5,#LO(___TBIBoingExit)
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ADD A0.3,A0.2,#TBICTX_DX /* DX Save area */
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ANDT D0Ar2,D0Ar2,#TBICTX_PRIV_BIT /* Extract PRIV bit */
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MOVT D0Ar6,#TBICTX_SOFT_BIT /* Only soft thread state */
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ADD D0Ar6,D0Ar6,D0Ar2 /* Add in PRIV bit if requested */
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SETL [A0.2],D0Ar6,D1Ar5 /* Push header fields */
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ADD D0FrT,A0.2,#TBICTX_AX /* Address AX save area */
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MSETL [A0.3],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
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MOV D0Ar6,#0
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MOV D1Ar5,#0
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SETL [A0.3++],D0Ar6,D1Ar5 /* Zero CT register states */
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SETL [A0.3++],D0Ar6,D1Ar5
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MSETL [D0FrT],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX regs */
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MOV A0FrP,A0.2 /* Restore me! */
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B ___TBIResume
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.size ___TBIASyncTrigger,.-___TBIASyncTrigger
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/*
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* Optimised return to handler for META Core
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*/
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___TBIBoingRTH:
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RTH /* Go to background level */
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MOVT A0.2, #HI($Lpcx_target)
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ADD A0.2,A0.2,#LO($Lpcx_target)
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MOV PCX,A0.2 /* Setup PCX for interrupts */
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MOV PC,D1Re0 /* Jump to handler */
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/*
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* This is where the code below needs to jump to wait for outermost interrupt
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* event in a non-privilege mode system (single shared interrupt stack).
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*/
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___TBIBoingPCX:
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MGETL A0StP,A0FrP,A0.2,A0.3 A0_4,[D1Re0] /* Restore AX regs */
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MOV TXSTATUS,D0Re0 /* Restore flags */
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GETL D0Re0,D1Re0,[D1Re0+#TBICTX_DX-TBICTX_BYTES]
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___TBIBoingRTI:
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RTI /* Wait for interrupt */
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$Lpcx_target:
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/*
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* Save initial interrupt state on current stack
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*/
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SETL [A0StP+#TBICTX_DX],D0Re0,D1Re0 /* Save key registers */
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ADD D1Re0,A0StP,#TBICTX_AX /* Address AX save area */
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MOV D0Re0,TXSTATUS /* Read TXSTATUS into D0Re0 */
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MOV TXSTATUS,#0 /* Clear TXSTATUS */
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MSETL [D1Re0],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX critical regs */
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/*
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* Register state at this point is-
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*
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* D0Re0 - Old TXSTATUS with PRIV and CBUF bits set if appropriate
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* A0StP - Is call stack frame and base of TBICTX being generated
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* A1GbP - Is valid static access link
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*/
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___TBIBoing:
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LOCK0 /* Make sure we have no locks! */
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ADD A1.2,A0StP,#TBICTX_DX+(8*1) /* Address DX.1 save area */
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MOV A0FrP,A0StP /* Setup frame pointer */
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MSETL [A1.2],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
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MOV D0Ar4,TXRPT /* Save critical CT regs */
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MOV D1Ar3,TXBPOBITS
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MOV D1Ar1,TXDIVTIME /* Calc catch buffer pSrc */
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MOV D0Ar2,TXMODE
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MOV TXMODE,#0 /* Clear TXMODE */
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#ifdef TXDIVTIME_RPDIRTY_BIT
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TSTT D1Ar1,#HI(TXDIVTIME_RPDIRTY_BIT)/* NZ = RPDIRTY */
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MOVT D0Ar6,#TBICTX_CBRP_BIT
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ORNZ D0Re0,D0Re0,D0Ar6 /* Set CBRP if RPDIRTY set */
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#endif
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MSETL [A1.2],D0Ar4,D0Ar2 /* Save CT regs state */
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MOV D0Ar2,D0Re0 /* Copy TXSTATUS */
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ANDMT D0Ar2,D0Ar2,#TBICTX_CBUF_BIT+TBICTX_CBRP_BIT
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#ifdef TBI_1_4
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MOVT D1Ar1,#TBICTX_FPAC_BIT /* Copy FPActive into FPAC */
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TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
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ORNZ D0Ar2,D0Ar2,D1Ar1
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#endif
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MOV D1Ar1,PCX /* Read CurrPC */
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ORT D0Ar2,D0Ar2,#TBICTX_CRIT_BIT /* SaveMask + CRIT bit */
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SETL [A0FrP+#TBICTX_Flags],D0Ar2,D1Ar1 /* Set pCtx header fields */
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/*
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* Completed context save, now we need to make a call to an interrupt handler
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*
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* D0Re0 - holds PRIV, WAIT, CBUF flags, HALT reason if appropriate
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* A0FrP - interrupt stack frame and base of TBICTX being generated
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* A0StP - same as A0FrP
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*/
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___TBIBoingWait:
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/* Reserve space for TBICTX and CBUF */
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ADD A0StP,A0StP,#TBICTX_BYTES+(CATCH_ENTRY_BYTES*CATCH_ENTRIES)
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MOV D0Ar4,TXSTATI /* Read the Triggers data */
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MOV D1Ar3,TXDIVTIME /* Read IRQEnc bits */
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MOV D0Ar2,D0Re0 /* Copy PRIV and WAIT flags */
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ANDT D0Ar2,D0Ar2,#TBICTX_PRIV_BIT+TBICTX_WAIT_BIT+TBICTX_CBUF_BIT
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#ifdef TBI_1_4
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MOVT D1Ar5,#TBICTX_FPAC_BIT /* Copy FPActive into FPAC */
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TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
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ORNZ D0Ar2,D0Ar2,D1Ar5
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#endif
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ANDT D1Ar3,D1Ar3,#HI(TXDIVTIME_IRQENC_BITS)
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LSR D1Ar3,D1Ar3,#TXDIVTIME_IRQENC_S
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AND TXSTATI,D0Ar4,#TXSTATI_BGNDHALT_BIT/* Ack any HALT seen */
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ANDS D0Ar4,D0Ar4,#0xFFFF-TXSTATI_BGNDHALT_BIT /* Only seen HALT? */
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ORT D0Ar2,D0Ar2,#TBICTX_CRIT_BIT /* Set CRIT */
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#ifndef BOOTROM
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MOVT A1LbP,#HI(___pTBIs)
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ADD A1LbP,A1LbP,#LO(___pTBIs)
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GETL D1Ar5,D0Ar6,[A1LbP] /* D0Ar6 = ___pTBIs[1] */
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#else
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/*
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* For BOOTROM support ___pTBIs must be allocated at offset 0 vs A1GbP
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*/
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GETL D1Ar5,D0Ar6,[A1GbP] /* D0Ar6 = ___pTBIs[1] */
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#endif
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BZ ___TBIBoingHalt /* Yes: Service HALT */
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/*
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* Encode interrupt as signal vector, strip away same/lower TXMASKI bits
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*/
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MOV D1Ar1,#1 /* Generate mask for this bit */
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MOV D0Re0,TXMASKI /* Get interrupt mask */
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LSL TXSTATI,D1Ar1,D1Ar3 /* Acknowledge trigger */
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AND TXMASKI,D0Re0,#TXSTATI_BGNDHALT_BIT /* Only allow HALTs */
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OR D0Ar2,D0Ar2,D0Re0 /* Set TBIRES.Sig.TrigMask */
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ADD D1Ar3,D1Ar3,#TBID_SIGNUM_TRT /* Offset into interrupt sigs */
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LSL D0Re0,D1Ar3,#TBID_SIGNUM_S /* Generate offset from SigNum */
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/*
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* This is a key moment we are about to call the handler, register state is
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* as follows-
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*
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* D0Re0 - Handler vector (SigNum<<TBID_SIGNUM_S)
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* D0Ar2 - TXMASKI:TBICTX_CRIT_BIT with optional CBUF and PRIV bits
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* D1Ar3 - SigNum
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* D0Ar4 - State read from TXSTATI
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* D1Ar5 - Inst for SWITCH trigger case only, otherwise undefined
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* D0Ar6 - pTBI
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*/
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___TBIBoingVec:
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ADD D0Re0,D0Re0,#TBI_fnSigs /* Offset into signal table */
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GETD D1Re0,[D0Ar6+D0Re0] /* Get address for Handler */
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/*
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* Call handler at interrupt level, when it returns simply resume execution
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* of state indicated by D1Re0.
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*/
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MOV D1Ar1,A0FrP /* Pass in pCtx */
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CALLR D1RtP,___TBIBoingRTH /* Use RTH to invoke handler */
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/*
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* Perform critical state restore and execute background thread.
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*
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* A0FrP - is pointer to TBICTX structure to resume
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* D0Re0 - contains additional TXMASKI triggers
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*/
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.text
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.balign 4
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#ifdef BOOTROM
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.global ___TBIResume
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#endif
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___TBIResume:
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/*
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* New META IP method
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*/
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RTH /* Go to interrupt level */
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MOV D0Ar4,TXMASKI /* Read TXMASKI */
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OR TXMASKI,D0Ar4,D0Re0 /* -Write-Modify TXMASKI */
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GETL D0Re0,D1Re0,[A0FrP+#TBICTX_Flags]/* Get Flags:SaveMask, CurrPC */
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MOV A0StP,A0FrP /* Position stack pointer */
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MOV D0Ar2,TXPOLLI /* Read pending triggers */
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MOV PCX,D1Re0 /* Set resumption PC */
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TST D0Ar2,#0xFFFF /* Any pending triggers? */
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BNZ ___TBIBoingWait /* Yes: Go for triggers */
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TSTT D0Re0,#TBICTX_WAIT_BIT /* Do we WAIT anyway? */
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BNZ ___TBIBoingWait /* Yes: Go for triggers */
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LSLS D1Ar5,D0Re0,#1 /* Test XCBF (MI) & PRIV (CS)? */
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ADD D1Re0,A0FrP,#TBICTX_CurrRPT /* Address CT save area */
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ADD A0StP,A0FrP,#TBICTX_DX+(8*1) /* Address DX.1 save area */
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MGETL A0.2,A0.3,[D1Re0] /* Get CT reg states */
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MOV D1Ar3,A1.3 /* Copy old TXDIVTIME */
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BPL ___TBIResCrit /* No: Skip logic */
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ADD D0Ar4,A0FrP,#TBICTX_BYTES /* Source is after TBICTX */
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ANDST D1Ar3,D1Ar3,#HI(TXDIVTIME_RPMASK_BITS)/* !Z if RPDIRTY */
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MGETL D0.5,D0.6,[D0Ar4] /* Read Catch state */
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MOV TXCATCH0,D0.5 /* Restore TXCATCHn */
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MOV TXCATCH1,D1.5
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MOV TXCATCH2,D0.6
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MOV TXCATCH3,D1.6
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BZ ___TBIResCrit
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MOV D0Ar2,#(1*8)
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LSRS D1Ar3,D1Ar3,#TXDIVTIME_RPMASK_S+1 /* 2nd RPMASK bit -> bit 0 */
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ADD RA,D0Ar4,#(0*8) /* Re-read read pipeline */
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ADDNZ RA,D0Ar4,D0Ar2 /* If Bit 0 set issue RA */
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LSRS D1Ar3,D1Ar3,#2 /* Bit 1 -> C, Bit 2 -> Bit 0 */
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ADD D0Ar2,D0Ar2,#8
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ADDCS RA,D0Ar4,D0Ar2 /* If C issue RA */
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ADD D0Ar2,D0Ar2,#8
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ADDNZ RA,D0Ar4,D0Ar2 /* If Bit 0 set issue RA */
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LSRS D1Ar3,D1Ar3,#2 /* Bit 1 -> C, Bit 2 -> Bit 0 */
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ADD D0Ar2,D0Ar2,#8
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ADDCS RA,D0Ar4,D0Ar2 /* If C issue RA */
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ADD D0Ar2,D0Ar2,#8
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ADDNZ RA,D0Ar4,D0Ar2 /* If Bit 0 set issue RA */
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MOV TXDIVTIME,A1.3 /* Set RPDIRTY again */
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___TBIResCrit:
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LSLS D1Ar5,D0Re0,#1 /* Test XCBF (MI) & PRIV (CS)? */
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#ifdef TBI_1_4
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ANDT D1Ar5,D1Ar5,#(TBICTX_FPAC_BIT*2)
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LSL D0Ar6,D1Ar5,#3 /* Convert FPAC into FPACTIVE */
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#endif
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ANDMT D0Re0,D0Re0,#TBICTX_CBUF_BIT /* Keep CBUF bit from SaveMask */
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#ifdef TBI_1_4
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OR D0Re0,D0Re0,D0Ar6 /* Combine FPACTIVE with others */
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#endif
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MGETL D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7,[A0StP] /* Restore DX */
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MOV TXRPT,A0.2 /* Restore CT regs */
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MOV TXBPOBITS,A1.2
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MOV TXMODE,A0.3
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BCC ___TBIBoingPCX /* Do non-PRIV wait! */
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MOV A1GblIGbP,A1GbP /* Save A1GbP too */
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MGETL A0StP,A0FrP,A0.2,A0.3 A0_4,[D1Re0] /* Restore AX regs */
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/*
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* Wait for the first interrupt/exception trigger in a privilege mode system
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* (interrupt stack area for current TASK to be pointed to by A0GblIStP
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* or per_cpu__stack_save[hwthread_id]).
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*/
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MOV TXSTATUS,D0Re0 /* Restore flags */
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MOV D0Re0,TXPRIVEXT /* Set TXPRIVEXT_TXTOGGLEI_BIT */
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SUB D1Re0,D1Re0,#TBICTX_BYTES /* TBICTX is top of int stack */
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#ifdef TBX_PERCPU_SP_SAVE
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SWAP D1Ar3,A1GbP
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MOV D1Ar3,TXENABLE /* Which thread are we? */
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AND D1Ar3,D1Ar3,#TXENABLE_THREAD_BITS
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LSR D1Ar3,D1Ar3,#TXENABLE_THREAD_S-2
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ADDT D1Ar3,D1Ar3,#HI(_per_cpu__stack_save)
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ADD D1Ar3,D1Ar3,#LO(_per_cpu__stack_save)
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SETD [D1Ar3],D1Re0
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SWAP D1Ar3,A1GbP
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#else
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MOV A0GblIStP, D1Re0
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#endif
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OR D0Re0,D0Re0,#TXPRIVEXT_TXTOGGLEI_BIT
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MOV TXPRIVEXT,D0Re0 /* Cannot set TXPRIVEXT if !priv */
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GETL D0Re0,D1Re0,[D1Re0+#TBICTX_DX]
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RTI /* Wait for interrupt */
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/*
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* Save initial interrupt state on A0GblIStP, switch to A0GblIStP if
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* BOOTROM code, save and switch to [A1GbP] otherwise.
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*/
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___TBIBoingPCXP:
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#ifdef TBX_PERCPU_SP_SAVE
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SWAP D1Ar3,A1GbP /* Get PRIV stack base */
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MOV D1Ar3,TXENABLE /* Which thread are we? */
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AND D1Ar3,D1Ar3,#TXENABLE_THREAD_BITS
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LSR D1Ar3,D1Ar3,#TXENABLE_THREAD_S-2
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ADDT D1Ar3,D1Ar3,#HI(_per_cpu__stack_save)
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ADD D1Ar3,D1Ar3,#LO(_per_cpu__stack_save)
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GETD D1Ar3,[D1Ar3]
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#else
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SWAP D1Ar3,A0GblIStP /* Get PRIV stack base */
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#endif
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SETL [D1Ar3+#TBICTX_DX],D0Re0,D1Re0 /* Save key registers */
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MOV D0Re0,TXPRIVEXT /* Clear TXPRIVEXT_TXTOGGLEI_BIT */
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ADD D1Re0,D1Ar3,#TBICTX_AX /* Address AX save area */
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ANDMB D0Re0,D0Re0,#0xFFFF-TXPRIVEXT_TXTOGGLEI_BIT
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MOV TXPRIVEXT,D0Re0 /* Cannot set TXPRIVEXT if !priv */
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MOV D0Re0,TXSTATUS /* Read TXSTATUS into D0Re0 */
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MOV TXSTATUS,#0 /* Clear TXSTATUS */
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MSETL [D1Re0],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX critical regs */
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MOV A0StP,D1Ar3 /* Switch stacks */
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#ifdef TBX_PERCPU_SP_SAVE
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MOV D1Ar3,A1GbP /* Get D1Ar2 back */
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#else
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MOV D1Ar3,A0GblIStP /* Get D1Ar2 back */
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#endif
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ORT D0Re0,D0Re0,#TBICTX_PRIV_BIT /* Add PRIV to TXSTATUS */
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MOV A1GbP,A1GblIGbP /* Restore A1GbP */
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B ___TBIBoing /* Enter common handler code */
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/*
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* At this point we know it's a background HALT case we are handling.
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* The restored TXSTATUS always needs to have zero in the reason bits.
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*/
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___TBIBoingHalt:
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MOV D0Ar4,TXMASKI /* Get interrupt mask */
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ANDST D0Re0,D0Re0,#HI(TXSTATUS_MAJOR_HALT_BITS+TXSTATUS_MEM_FAULT_BITS)
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AND TXMASKI,D0Ar4,#TXSTATI_BGNDHALT_BIT /* Only allow HALTs */
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AND D0Ar4,D0Ar4,#0xFFFF-TXSTATI_BGNDHALT_BIT /* What ints are off? */
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OR D0Ar2,D0Ar2,D0Ar4 /* Set TBIRES.Sig.TrigMask */
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|
MOV D0Ar4,#TXSTATI_BGNDHALT_BIT /* This was the trigger state */
|
|
LSR D1Ar3,D0Re0,#TXSTATUS_MAJOR_HALT_S
|
|
MOV D0Re0,#TBID_SIGNUM_XXF<<TBID_SIGNUM_S
|
|
BNZ ___TBIBoingVec /* Jump to XXF exception handler */
|
|
/*
|
|
* Only the SWITCH cases are left, PCX must be valid
|
|
*/
|
|
#ifdef TBI_1_4
|
|
MOV D1Ar5,TXPRIVEXT
|
|
TST D1Ar5,#TXPRIVEXT_MINIMON_BIT
|
|
LSR D1Ar3,D1Ar1,#1 /* Shift needed for MINIM paths (fill stall) */
|
|
BZ $Lmeta /* If META only, skip */
|
|
TSTT D1Ar1,#HI(0x00800000)
|
|
ANDMT D1Ar3,D1Ar3,#HI(0x007FFFFF >> 1)/* Shifted mask for large MINIM */
|
|
ANDT D1Ar1,D1Ar1,#HI(0xFFE00000) /* Static mask for small MINIM */
|
|
BZ $Llarge_minim /* If large MINIM */
|
|
$Lsmall_minim:
|
|
TSTT D1Ar3,#HI(0x00100000 >> 1)
|
|
ANDMT D1Ar3,D1Ar3,#HI(0x001FFFFF >> 1)/* Correct shifted mask for large MINIM */
|
|
ADDZ D1Ar1,D1Ar1,D1Ar3 /* If META rgn, add twice to undo LSR #1 */
|
|
B $Lrecombine
|
|
$Llarge_minim:
|
|
ANDST D1Ar1,D1Ar1,#HI(0xFF800000) /* Correct static mask for small MINIM */
|
|
/* Z=0 (Cannot place code at NULL) */
|
|
$Lrecombine:
|
|
ADD D1Ar1,D1Ar1,D1Ar3 /* Combine static and shifted parts */
|
|
$Lmeta:
|
|
GETW D1Ar5,[D1Ar1++] /* META: lo-16, MINIM: lo-16 (all-16 if short) */
|
|
GETW D1Ar3,[D1Ar1] /* META: hi-16, MINIM: hi-16 (only if long) */
|
|
MOV D1Re0,D1Ar5
|
|
XOR D1Re0,D1Re0,#0x4000
|
|
LSLSNZ D1Re0,D1Re0,#(32-14) /* MINIM: If long C=0, if short C=1 */
|
|
LSLCC D1Ar3,D1Ar3,#16 /* META/MINIM long: Move hi-16 up */
|
|
LSLCS D1Ar3,D1Ar5,#16 /* MINIM short: Dup all-16 */
|
|
ADD D1Ar5,D1Ar5,D1Ar3 /* ALL: Combine both 16-bit parts */
|
|
#else
|
|
GETD D1Ar5,[D1Ar1] /* Read instruction for switch */
|
|
#endif
|
|
LSR D1Ar3,D1Ar5,#22 /* Convert into signal number */
|
|
AND D1Ar3,D1Ar3,#TBID_SIGNUM_SW3-TBID_SIGNUM_SW0
|
|
LSL D0Re0,D1Ar3,#TBID_SIGNUM_S /* Generate offset from SigNum */
|
|
B ___TBIBoingVec /* Jump to switch handler */
|
|
/*
|
|
* Exit from TBIASyncTrigger call
|
|
*/
|
|
___TBIBoingExit:
|
|
GETL D0FrT,D1RtP,[A0FrP++] /* Restore state from frame */
|
|
SUB A0StP,A0FrP,#8 /* Unwind stack */
|
|
MOV A0FrP,D0FrT /* Last memory read completes */
|
|
MOV PC,D1RtP /* Return to caller */
|
|
#endif /* ifdef CODE_USES_BOOTROM */
|
|
.size ___TBIResume,.-___TBIResume
|
|
|
|
#ifndef BOOTROM
|
|
/*
|
|
* void __TBIASyncResume( TBIRES State )
|
|
*/
|
|
.text
|
|
.balign 4
|
|
.global ___TBIASyncResume
|
|
.type ___TBIASyncResume,function
|
|
___TBIASyncResume:
|
|
/*
|
|
* Perform CRIT|SOFT state restore and execute background thread.
|
|
*/
|
|
MOV D1Ar3,D1Ar1 /* Restore this context */
|
|
MOV D0Re0,D0Ar2 /* Carry in additional triggers */
|
|
/* Reserve space for TBICTX */
|
|
ADD D1Ar3,D1Ar3,#TBICTX_BYTES+(CATCH_ENTRY_BYTES*CATCH_ENTRIES)
|
|
MOV A0StP,D1Ar3 /* Enter with protection of */
|
|
MOV A0FrP,D1Ar1 /* TBICTX on our stack */
|
|
#ifdef CODE_USES_BOOTROM
|
|
MOVT D1Ar1,#HI(LINCORE_BASE)
|
|
JUMP D1Ar1,#0xA4
|
|
#else
|
|
B ___TBIResume
|
|
#endif
|
|
.size ___TBIASyncResume,.-___TBIASyncResume
|
|
#endif /* ifndef BOOTROM */
|
|
|
|
/*
|
|
* End of tbipcx.S
|
|
*/
|