![Stephen Hemminger](/assets/img/avatar_default.png)
This patch moves neigh_setup and hard_start_xmit into the network device ops structure. For bisection, fix all the previously converted drivers as well. Bonding driver took the biggest hit on this. Added a prefetch of the hard_start_xmit in the fast path to try and reduce any impact this would have. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2104 lines
54 KiB
C
2104 lines
54 KiB
C
/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
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/*
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Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
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Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
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Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
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Copyright 2001 Manfred Spraul [natsemi.c]
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Copyright 1999-2001 by Donald Becker. [natsemi.c]
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Written 1997-2001 by Donald Becker. [8139too.c]
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Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
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This software may be used and distributed according to the terms of
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the GNU General Public License (GPL), incorporated herein by reference.
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Drivers based on or derived from this code fall under the GPL and must
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retain the authorship, copyright and license notice. This file is not
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a complete program and may only be used when the entire operating
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system is licensed under the GPL.
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See the file COPYING in this distribution for more information.
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Contributors:
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Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
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PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
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LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
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TODO:
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* Test Tx checksumming thoroughly
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Low priority TODO:
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* Complete reset on PciErr
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* Consider Rx interrupt mitigation using TimerIntr
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* Investigate using skb->priority with h/w VLAN priority
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* Investigate using High Priority Tx Queue with skb->priority
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* Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
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* Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
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* Implement Tx software interrupt mitigation via
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Tx descriptor bit
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* The real minimum of CP_MIN_MTU is 4 bytes. However,
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for this to be supported, one must(?) turn on packet padding.
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* Support external MII transceivers (patch available)
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NOTES:
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* TX checksumming is considered experimental. It is off by
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default, use ethtool to turn it on.
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*/
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#define DRV_NAME "8139cp"
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#define DRV_VERSION "1.3"
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#define DRV_RELDATE "Mar 22, 2004"
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include <linux/if_vlan.h>
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#include <linux/crc32.h>
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#include <linux/in.h>
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#include <linux/ip.h>
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#include <linux/tcp.h>
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#include <linux/udp.h>
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#include <linux/cache.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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/* VLAN tagging feature enable/disable */
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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
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#define CP_VLAN_TAG_USED 1
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#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
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do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
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#else
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#define CP_VLAN_TAG_USED 0
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#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
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do { (tx_desc)->opts2 = 0; } while (0)
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#endif
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/* These identify the driver base version and may not be removed. */
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static char version[] =
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KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
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MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
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MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
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MODULE_VERSION(DRV_VERSION);
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MODULE_LICENSE("GPL");
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static int debug = -1;
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module_param(debug, int, 0);
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MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
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/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
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The RTL chips use a 64 element hash table based on the Ethernet CRC. */
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static int multicast_filter_limit = 32;
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module_param(multicast_filter_limit, int, 0);
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MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
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#define PFX DRV_NAME ": "
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#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
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NETIF_MSG_PROBE | \
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NETIF_MSG_LINK)
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#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
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#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
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#define CP_REGS_SIZE (0xff + 1)
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#define CP_REGS_VER 1 /* version 1 */
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#define CP_RX_RING_SIZE 64
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#define CP_TX_RING_SIZE 64
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#define CP_RING_BYTES \
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((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
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(sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
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CP_STATS_SIZE)
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#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
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#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
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#define TX_BUFFS_AVAIL(CP) \
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(((CP)->tx_tail <= (CP)->tx_head) ? \
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(CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
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(CP)->tx_tail - (CP)->tx_head - 1)
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#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
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#define CP_INTERNAL_PHY 32
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/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
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#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
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#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
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#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
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#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
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/* Time in jiffies before concluding the transmitter is hung. */
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#define TX_TIMEOUT (6*HZ)
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/* hardware minimum and maximum for a single frame's data payload */
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#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
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#define CP_MAX_MTU 4096
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enum {
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/* NIC register offsets */
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MAC0 = 0x00, /* Ethernet hardware address. */
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MAR0 = 0x08, /* Multicast filter. */
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StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
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TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
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HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
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Cmd = 0x37, /* Command register */
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IntrMask = 0x3C, /* Interrupt mask */
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IntrStatus = 0x3E, /* Interrupt status */
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TxConfig = 0x40, /* Tx configuration */
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ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
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RxConfig = 0x44, /* Rx configuration */
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RxMissed = 0x4C, /* 24 bits valid, write clears */
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Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
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Config1 = 0x52, /* Config1 */
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Config3 = 0x59, /* Config3 */
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Config4 = 0x5A, /* Config4 */
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MultiIntr = 0x5C, /* Multiple interrupt select */
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BasicModeCtrl = 0x62, /* MII BMCR */
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BasicModeStatus = 0x64, /* MII BMSR */
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NWayAdvert = 0x66, /* MII ADVERTISE */
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NWayLPAR = 0x68, /* MII LPA */
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NWayExpansion = 0x6A, /* MII Expansion */
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Config5 = 0xD8, /* Config5 */
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TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
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RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
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CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
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IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
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RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
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TxThresh = 0xEC, /* Early Tx threshold */
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OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
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OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
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/* Tx and Rx status descriptors */
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DescOwn = (1 << 31), /* Descriptor is owned by NIC */
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RingEnd = (1 << 30), /* End of descriptor ring */
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FirstFrag = (1 << 29), /* First segment of a packet */
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LastFrag = (1 << 28), /* Final segment of a packet */
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LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
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MSSShift = 16, /* MSS value position */
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MSSMask = 0xfff, /* MSS value: 11 bits */
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TxError = (1 << 23), /* Tx error summary */
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RxError = (1 << 20), /* Rx error summary */
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IPCS = (1 << 18), /* Calculate IP checksum */
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UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
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TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
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TxVlanTag = (1 << 17), /* Add VLAN tag */
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RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
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IPFail = (1 << 15), /* IP checksum failed */
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UDPFail = (1 << 14), /* UDP/IP checksum failed */
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TCPFail = (1 << 13), /* TCP/IP checksum failed */
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NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
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PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
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PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
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RxProtoTCP = 1,
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RxProtoUDP = 2,
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RxProtoIP = 3,
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TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
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TxOWC = (1 << 22), /* Tx Out-of-window collision */
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TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
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TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
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TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
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TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
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RxErrFrame = (1 << 27), /* Rx frame alignment error */
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RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
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RxErrCRC = (1 << 18), /* Rx CRC error */
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RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
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RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
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RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
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/* StatsAddr register */
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DumpStats = (1 << 3), /* Begin stats dump */
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/* RxConfig register */
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RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
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RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
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AcceptErr = 0x20, /* Accept packets with CRC errors */
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AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
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AcceptBroadcast = 0x08, /* Accept broadcast packets */
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AcceptMulticast = 0x04, /* Accept multicast packets */
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AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
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AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
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/* IntrMask / IntrStatus registers */
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PciErr = (1 << 15), /* System error on the PCI bus */
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TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
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LenChg = (1 << 13), /* Cable length change */
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SWInt = (1 << 8), /* Software-requested interrupt */
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TxEmpty = (1 << 7), /* No Tx descriptors available */
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RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
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LinkChg = (1 << 5), /* Packet underrun, or link change */
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RxEmpty = (1 << 4), /* No Rx descriptors available */
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TxErr = (1 << 3), /* Tx error */
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TxOK = (1 << 2), /* Tx packet sent */
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RxErr = (1 << 1), /* Rx error */
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RxOK = (1 << 0), /* Rx packet received */
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IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
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but hardware likes to raise it */
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IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
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RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
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RxErr | RxOK | IntrResvd,
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/* C mode command register */
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CmdReset = (1 << 4), /* Enable to reset; self-clearing */
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RxOn = (1 << 3), /* Rx mode enable */
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TxOn = (1 << 2), /* Tx mode enable */
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/* C+ mode command register */
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RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
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RxChkSum = (1 << 5), /* Rx checksum offload enable */
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PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
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PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
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CpRxOn = (1 << 1), /* Rx mode enable */
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CpTxOn = (1 << 0), /* Tx mode enable */
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/* Cfg9436 EEPROM control register */
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Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
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Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
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/* TxConfig register */
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IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
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TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
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/* Early Tx Threshold register */
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TxThreshMask = 0x3f, /* Mask bits 5-0 */
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TxThreshMax = 2048, /* Max early Tx threshold */
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/* Config1 register */
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DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
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LWACT = (1 << 4), /* LWAKE active mode */
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PMEnable = (1 << 0), /* Enable various PM features of chip */
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/* Config3 register */
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PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
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MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
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LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
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/* Config4 register */
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LWPTN = (1 << 1), /* LWAKE Pattern */
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LWPME = (1 << 4), /* LANWAKE vs PMEB */
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/* Config5 register */
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BWF = (1 << 6), /* Accept Broadcast wakeup frame */
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MWF = (1 << 5), /* Accept Multicast wakeup frame */
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UWF = (1 << 4), /* Accept Unicast wakeup frame */
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LANWake = (1 << 1), /* Enable LANWake signal */
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PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
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cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
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cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
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cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
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};
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static const unsigned int cp_rx_config =
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(RX_FIFO_THRESH << RxCfgFIFOShift) |
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(RX_DMA_BURST << RxCfgDMAShift);
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struct cp_desc {
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__le32 opts1;
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__le32 opts2;
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__le64 addr;
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};
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struct cp_dma_stats {
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__le64 tx_ok;
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__le64 rx_ok;
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__le64 tx_err;
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__le32 rx_err;
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__le16 rx_fifo;
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__le16 frame_align;
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__le32 tx_ok_1col;
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__le32 tx_ok_mcol;
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__le64 rx_ok_phys;
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__le64 rx_ok_bcast;
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__le32 rx_ok_mcast;
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__le16 tx_abort;
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__le16 tx_underrun;
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} __attribute__((packed));
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struct cp_extra_stats {
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unsigned long rx_frags;
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};
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struct cp_private {
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void __iomem *regs;
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struct net_device *dev;
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spinlock_t lock;
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u32 msg_enable;
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struct napi_struct napi;
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struct pci_dev *pdev;
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u32 rx_config;
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u16 cpcmd;
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struct cp_extra_stats cp_stats;
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unsigned rx_head ____cacheline_aligned;
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unsigned rx_tail;
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struct cp_desc *rx_ring;
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struct sk_buff *rx_skb[CP_RX_RING_SIZE];
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unsigned tx_head ____cacheline_aligned;
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unsigned tx_tail;
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struct cp_desc *tx_ring;
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struct sk_buff *tx_skb[CP_TX_RING_SIZE];
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unsigned rx_buf_sz;
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unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
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#if CP_VLAN_TAG_USED
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struct vlan_group *vlgrp;
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#endif
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dma_addr_t ring_dma;
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struct mii_if_info mii_if;
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};
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#define cpr8(reg) readb(cp->regs + (reg))
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#define cpr16(reg) readw(cp->regs + (reg))
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#define cpr32(reg) readl(cp->regs + (reg))
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#define cpw8(reg,val) writeb((val), cp->regs + (reg))
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#define cpw16(reg,val) writew((val), cp->regs + (reg))
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#define cpw32(reg,val) writel((val), cp->regs + (reg))
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#define cpw8_f(reg,val) do { \
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writeb((val), cp->regs + (reg)); \
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readb(cp->regs + (reg)); \
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} while (0)
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#define cpw16_f(reg,val) do { \
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writew((val), cp->regs + (reg)); \
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readw(cp->regs + (reg)); \
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} while (0)
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#define cpw32_f(reg,val) do { \
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writel((val), cp->regs + (reg)); \
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readl(cp->regs + (reg)); \
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} while (0)
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static void __cp_set_rx_mode (struct net_device *dev);
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static void cp_tx (struct cp_private *cp);
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static void cp_clean_rings (struct cp_private *cp);
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#ifdef CONFIG_NET_POLL_CONTROLLER
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static void cp_poll_controller(struct net_device *dev);
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#endif
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static int cp_get_eeprom_len(struct net_device *dev);
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static int cp_get_eeprom(struct net_device *dev,
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struct ethtool_eeprom *eeprom, u8 *data);
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static int cp_set_eeprom(struct net_device *dev,
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struct ethtool_eeprom *eeprom, u8 *data);
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static struct pci_device_id cp_pci_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
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{ PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
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{ },
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};
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MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
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static struct {
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const char str[ETH_GSTRING_LEN];
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} ethtool_stats_keys[] = {
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{ "tx_ok" },
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{ "rx_ok" },
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{ "tx_err" },
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{ "rx_err" },
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{ "rx_fifo" },
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{ "frame_align" },
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|
{ "tx_ok_1col" },
|
|
{ "tx_ok_mcol" },
|
|
{ "rx_ok_phys" },
|
|
{ "rx_ok_bcast" },
|
|
{ "rx_ok_mcast" },
|
|
{ "tx_abort" },
|
|
{ "tx_underrun" },
|
|
{ "rx_frags" },
|
|
};
|
|
|
|
|
|
#if CP_VLAN_TAG_USED
|
|
static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
cp->vlgrp = grp;
|
|
if (grp)
|
|
cp->cpcmd |= RxVlanOn;
|
|
else
|
|
cp->cpcmd &= ~RxVlanOn;
|
|
|
|
cpw16(CpCmd, cp->cpcmd);
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
}
|
|
#endif /* CP_VLAN_TAG_USED */
|
|
|
|
static inline void cp_set_rxbufsize (struct cp_private *cp)
|
|
{
|
|
unsigned int mtu = cp->dev->mtu;
|
|
|
|
if (mtu > ETH_DATA_LEN)
|
|
/* MTU + ethernet header + FCS + optional VLAN tag */
|
|
cp->rx_buf_sz = mtu + ETH_HLEN + 8;
|
|
else
|
|
cp->rx_buf_sz = PKT_BUF_SZ;
|
|
}
|
|
|
|
static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
|
|
struct cp_desc *desc)
|
|
{
|
|
skb->protocol = eth_type_trans (skb, cp->dev);
|
|
|
|
cp->dev->stats.rx_packets++;
|
|
cp->dev->stats.rx_bytes += skb->len;
|
|
|
|
#if CP_VLAN_TAG_USED
|
|
if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
|
|
vlan_hwaccel_receive_skb(skb, cp->vlgrp,
|
|
swab16(le32_to_cpu(desc->opts2) & 0xffff));
|
|
} else
|
|
#endif
|
|
netif_receive_skb(skb);
|
|
}
|
|
|
|
static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
|
|
u32 status, u32 len)
|
|
{
|
|
if (netif_msg_rx_err (cp))
|
|
printk (KERN_DEBUG
|
|
"%s: rx err, slot %d status 0x%x len %d\n",
|
|
cp->dev->name, rx_tail, status, len);
|
|
cp->dev->stats.rx_errors++;
|
|
if (status & RxErrFrame)
|
|
cp->dev->stats.rx_frame_errors++;
|
|
if (status & RxErrCRC)
|
|
cp->dev->stats.rx_crc_errors++;
|
|
if ((status & RxErrRunt) || (status & RxErrLong))
|
|
cp->dev->stats.rx_length_errors++;
|
|
if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
|
|
cp->dev->stats.rx_length_errors++;
|
|
if (status & RxErrFIFO)
|
|
cp->dev->stats.rx_fifo_errors++;
|
|
}
|
|
|
|
static inline unsigned int cp_rx_csum_ok (u32 status)
|
|
{
|
|
unsigned int protocol = (status >> 16) & 0x3;
|
|
|
|
if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
|
|
return 1;
|
|
else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
|
|
return 1;
|
|
else if ((protocol == RxProtoIP) && (!(status & IPFail)))
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
static int cp_rx_poll(struct napi_struct *napi, int budget)
|
|
{
|
|
struct cp_private *cp = container_of(napi, struct cp_private, napi);
|
|
struct net_device *dev = cp->dev;
|
|
unsigned int rx_tail = cp->rx_tail;
|
|
int rx;
|
|
|
|
rx_status_loop:
|
|
rx = 0;
|
|
cpw16(IntrStatus, cp_rx_intr_mask);
|
|
|
|
while (1) {
|
|
u32 status, len;
|
|
dma_addr_t mapping;
|
|
struct sk_buff *skb, *new_skb;
|
|
struct cp_desc *desc;
|
|
unsigned buflen;
|
|
|
|
skb = cp->rx_skb[rx_tail];
|
|
BUG_ON(!skb);
|
|
|
|
desc = &cp->rx_ring[rx_tail];
|
|
status = le32_to_cpu(desc->opts1);
|
|
if (status & DescOwn)
|
|
break;
|
|
|
|
len = (status & 0x1fff) - 4;
|
|
mapping = le64_to_cpu(desc->addr);
|
|
|
|
if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
|
|
/* we don't support incoming fragmented frames.
|
|
* instead, we attempt to ensure that the
|
|
* pre-allocated RX skbs are properly sized such
|
|
* that RX fragments are never encountered
|
|
*/
|
|
cp_rx_err_acct(cp, rx_tail, status, len);
|
|
dev->stats.rx_dropped++;
|
|
cp->cp_stats.rx_frags++;
|
|
goto rx_next;
|
|
}
|
|
|
|
if (status & (RxError | RxErrFIFO)) {
|
|
cp_rx_err_acct(cp, rx_tail, status, len);
|
|
goto rx_next;
|
|
}
|
|
|
|
if (netif_msg_rx_status(cp))
|
|
printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
|
|
dev->name, rx_tail, status, len);
|
|
|
|
buflen = cp->rx_buf_sz + NET_IP_ALIGN;
|
|
new_skb = netdev_alloc_skb(dev, buflen);
|
|
if (!new_skb) {
|
|
dev->stats.rx_dropped++;
|
|
goto rx_next;
|
|
}
|
|
|
|
skb_reserve(new_skb, NET_IP_ALIGN);
|
|
|
|
dma_unmap_single(&cp->pdev->dev, mapping,
|
|
buflen, PCI_DMA_FROMDEVICE);
|
|
|
|
/* Handle checksum offloading for incoming packets. */
|
|
if (cp_rx_csum_ok(status))
|
|
skb->ip_summed = CHECKSUM_UNNECESSARY;
|
|
else
|
|
skb->ip_summed = CHECKSUM_NONE;
|
|
|
|
skb_put(skb, len);
|
|
|
|
mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
|
|
PCI_DMA_FROMDEVICE);
|
|
cp->rx_skb[rx_tail] = new_skb;
|
|
|
|
cp_rx_skb(cp, skb, desc);
|
|
rx++;
|
|
|
|
rx_next:
|
|
cp->rx_ring[rx_tail].opts2 = 0;
|
|
cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
|
|
if (rx_tail == (CP_RX_RING_SIZE - 1))
|
|
desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
|
|
cp->rx_buf_sz);
|
|
else
|
|
desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
|
|
rx_tail = NEXT_RX(rx_tail);
|
|
|
|
if (rx >= budget)
|
|
break;
|
|
}
|
|
|
|
cp->rx_tail = rx_tail;
|
|
|
|
/* if we did not reach work limit, then we're done with
|
|
* this round of polling
|
|
*/
|
|
if (rx < budget) {
|
|
unsigned long flags;
|
|
|
|
if (cpr16(IntrStatus) & cp_rx_intr_mask)
|
|
goto rx_status_loop;
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
cpw16_f(IntrMask, cp_intr_mask);
|
|
__netif_rx_complete(dev, napi);
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
}
|
|
|
|
return rx;
|
|
}
|
|
|
|
static irqreturn_t cp_interrupt (int irq, void *dev_instance)
|
|
{
|
|
struct net_device *dev = dev_instance;
|
|
struct cp_private *cp;
|
|
u16 status;
|
|
|
|
if (unlikely(dev == NULL))
|
|
return IRQ_NONE;
|
|
cp = netdev_priv(dev);
|
|
|
|
status = cpr16(IntrStatus);
|
|
if (!status || (status == 0xFFFF))
|
|
return IRQ_NONE;
|
|
|
|
if (netif_msg_intr(cp))
|
|
printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
|
|
dev->name, status, cpr8(Cmd), cpr16(CpCmd));
|
|
|
|
cpw16(IntrStatus, status & ~cp_rx_intr_mask);
|
|
|
|
spin_lock(&cp->lock);
|
|
|
|
/* close possible race's with dev_close */
|
|
if (unlikely(!netif_running(dev))) {
|
|
cpw16(IntrMask, 0);
|
|
spin_unlock(&cp->lock);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
|
|
if (netif_rx_schedule_prep(dev, &cp->napi)) {
|
|
cpw16_f(IntrMask, cp_norx_intr_mask);
|
|
__netif_rx_schedule(dev, &cp->napi);
|
|
}
|
|
|
|
if (status & (TxOK | TxErr | TxEmpty | SWInt))
|
|
cp_tx(cp);
|
|
if (status & LinkChg)
|
|
mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
|
|
|
|
spin_unlock(&cp->lock);
|
|
|
|
if (status & PciErr) {
|
|
u16 pci_status;
|
|
|
|
pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
|
|
pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
|
|
printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
|
|
dev->name, status, pci_status);
|
|
|
|
/* TODO: reset hardware */
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
/*
|
|
* Polling receive - used by netconsole and other diagnostic tools
|
|
* to allow network i/o with interrupts disabled.
|
|
*/
|
|
static void cp_poll_controller(struct net_device *dev)
|
|
{
|
|
disable_irq(dev->irq);
|
|
cp_interrupt(dev->irq, dev);
|
|
enable_irq(dev->irq);
|
|
}
|
|
#endif
|
|
|
|
static void cp_tx (struct cp_private *cp)
|
|
{
|
|
unsigned tx_head = cp->tx_head;
|
|
unsigned tx_tail = cp->tx_tail;
|
|
|
|
while (tx_tail != tx_head) {
|
|
struct cp_desc *txd = cp->tx_ring + tx_tail;
|
|
struct sk_buff *skb;
|
|
u32 status;
|
|
|
|
rmb();
|
|
status = le32_to_cpu(txd->opts1);
|
|
if (status & DescOwn)
|
|
break;
|
|
|
|
skb = cp->tx_skb[tx_tail];
|
|
BUG_ON(!skb);
|
|
|
|
dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
|
|
le32_to_cpu(txd->opts1) & 0xffff,
|
|
PCI_DMA_TODEVICE);
|
|
|
|
if (status & LastFrag) {
|
|
if (status & (TxError | TxFIFOUnder)) {
|
|
if (netif_msg_tx_err(cp))
|
|
printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
|
|
cp->dev->name, status);
|
|
cp->dev->stats.tx_errors++;
|
|
if (status & TxOWC)
|
|
cp->dev->stats.tx_window_errors++;
|
|
if (status & TxMaxCol)
|
|
cp->dev->stats.tx_aborted_errors++;
|
|
if (status & TxLinkFail)
|
|
cp->dev->stats.tx_carrier_errors++;
|
|
if (status & TxFIFOUnder)
|
|
cp->dev->stats.tx_fifo_errors++;
|
|
} else {
|
|
cp->dev->stats.collisions +=
|
|
((status >> TxColCntShift) & TxColCntMask);
|
|
cp->dev->stats.tx_packets++;
|
|
cp->dev->stats.tx_bytes += skb->len;
|
|
if (netif_msg_tx_done(cp))
|
|
printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
|
|
}
|
|
dev_kfree_skb_irq(skb);
|
|
}
|
|
|
|
cp->tx_skb[tx_tail] = NULL;
|
|
|
|
tx_tail = NEXT_TX(tx_tail);
|
|
}
|
|
|
|
cp->tx_tail = tx_tail;
|
|
|
|
if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
|
|
netif_wake_queue(cp->dev);
|
|
}
|
|
|
|
static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned entry;
|
|
u32 eor, flags;
|
|
unsigned long intr_flags;
|
|
#if CP_VLAN_TAG_USED
|
|
u32 vlan_tag = 0;
|
|
#endif
|
|
int mss = 0;
|
|
|
|
spin_lock_irqsave(&cp->lock, intr_flags);
|
|
|
|
/* This is a hard error, log it. */
|
|
if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
|
|
netif_stop_queue(dev);
|
|
spin_unlock_irqrestore(&cp->lock, intr_flags);
|
|
printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
|
|
dev->name);
|
|
return 1;
|
|
}
|
|
|
|
#if CP_VLAN_TAG_USED
|
|
if (cp->vlgrp && vlan_tx_tag_present(skb))
|
|
vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
|
|
#endif
|
|
|
|
entry = cp->tx_head;
|
|
eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
|
|
if (dev->features & NETIF_F_TSO)
|
|
mss = skb_shinfo(skb)->gso_size;
|
|
|
|
if (skb_shinfo(skb)->nr_frags == 0) {
|
|
struct cp_desc *txd = &cp->tx_ring[entry];
|
|
u32 len;
|
|
dma_addr_t mapping;
|
|
|
|
len = skb->len;
|
|
mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
|
|
CP_VLAN_TX_TAG(txd, vlan_tag);
|
|
txd->addr = cpu_to_le64(mapping);
|
|
wmb();
|
|
|
|
flags = eor | len | DescOwn | FirstFrag | LastFrag;
|
|
|
|
if (mss)
|
|
flags |= LargeSend | ((mss & MSSMask) << MSSShift);
|
|
else if (skb->ip_summed == CHECKSUM_PARTIAL) {
|
|
const struct iphdr *ip = ip_hdr(skb);
|
|
if (ip->protocol == IPPROTO_TCP)
|
|
flags |= IPCS | TCPCS;
|
|
else if (ip->protocol == IPPROTO_UDP)
|
|
flags |= IPCS | UDPCS;
|
|
else
|
|
WARN_ON(1); /* we need a WARN() */
|
|
}
|
|
|
|
txd->opts1 = cpu_to_le32(flags);
|
|
wmb();
|
|
|
|
cp->tx_skb[entry] = skb;
|
|
entry = NEXT_TX(entry);
|
|
} else {
|
|
struct cp_desc *txd;
|
|
u32 first_len, first_eor;
|
|
dma_addr_t first_mapping;
|
|
int frag, first_entry = entry;
|
|
const struct iphdr *ip = ip_hdr(skb);
|
|
|
|
/* We must give this initial chunk to the device last.
|
|
* Otherwise we could race with the device.
|
|
*/
|
|
first_eor = eor;
|
|
first_len = skb_headlen(skb);
|
|
first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
|
|
first_len, PCI_DMA_TODEVICE);
|
|
cp->tx_skb[entry] = skb;
|
|
entry = NEXT_TX(entry);
|
|
|
|
for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
|
|
skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
|
|
u32 len;
|
|
u32 ctrl;
|
|
dma_addr_t mapping;
|
|
|
|
len = this_frag->size;
|
|
mapping = dma_map_single(&cp->pdev->dev,
|
|
((void *) page_address(this_frag->page) +
|
|
this_frag->page_offset),
|
|
len, PCI_DMA_TODEVICE);
|
|
eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
|
|
|
|
ctrl = eor | len | DescOwn;
|
|
|
|
if (mss)
|
|
ctrl |= LargeSend |
|
|
((mss & MSSMask) << MSSShift);
|
|
else if (skb->ip_summed == CHECKSUM_PARTIAL) {
|
|
if (ip->protocol == IPPROTO_TCP)
|
|
ctrl |= IPCS | TCPCS;
|
|
else if (ip->protocol == IPPROTO_UDP)
|
|
ctrl |= IPCS | UDPCS;
|
|
else
|
|
BUG();
|
|
}
|
|
|
|
if (frag == skb_shinfo(skb)->nr_frags - 1)
|
|
ctrl |= LastFrag;
|
|
|
|
txd = &cp->tx_ring[entry];
|
|
CP_VLAN_TX_TAG(txd, vlan_tag);
|
|
txd->addr = cpu_to_le64(mapping);
|
|
wmb();
|
|
|
|
txd->opts1 = cpu_to_le32(ctrl);
|
|
wmb();
|
|
|
|
cp->tx_skb[entry] = skb;
|
|
entry = NEXT_TX(entry);
|
|
}
|
|
|
|
txd = &cp->tx_ring[first_entry];
|
|
CP_VLAN_TX_TAG(txd, vlan_tag);
|
|
txd->addr = cpu_to_le64(first_mapping);
|
|
wmb();
|
|
|
|
if (skb->ip_summed == CHECKSUM_PARTIAL) {
|
|
if (ip->protocol == IPPROTO_TCP)
|
|
txd->opts1 = cpu_to_le32(first_eor | first_len |
|
|
FirstFrag | DescOwn |
|
|
IPCS | TCPCS);
|
|
else if (ip->protocol == IPPROTO_UDP)
|
|
txd->opts1 = cpu_to_le32(first_eor | first_len |
|
|
FirstFrag | DescOwn |
|
|
IPCS | UDPCS);
|
|
else
|
|
BUG();
|
|
} else
|
|
txd->opts1 = cpu_to_le32(first_eor | first_len |
|
|
FirstFrag | DescOwn);
|
|
wmb();
|
|
}
|
|
cp->tx_head = entry;
|
|
if (netif_msg_tx_queued(cp))
|
|
printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
|
|
dev->name, entry, skb->len);
|
|
if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
|
|
netif_stop_queue(dev);
|
|
|
|
spin_unlock_irqrestore(&cp->lock, intr_flags);
|
|
|
|
cpw8(TxPoll, NormalTxPoll);
|
|
dev->trans_start = jiffies;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Set or clear the multicast filter for this adaptor.
|
|
This routine is not state sensitive and need not be SMP locked. */
|
|
|
|
static void __cp_set_rx_mode (struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
u32 mc_filter[2]; /* Multicast hash filter */
|
|
int i, rx_mode;
|
|
u32 tmp;
|
|
|
|
/* Note: do not reorder, GCC is clever about common statements. */
|
|
if (dev->flags & IFF_PROMISC) {
|
|
/* Unconditionally log net taps. */
|
|
rx_mode =
|
|
AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
|
|
AcceptAllPhys;
|
|
mc_filter[1] = mc_filter[0] = 0xffffffff;
|
|
} else if ((dev->mc_count > multicast_filter_limit)
|
|
|| (dev->flags & IFF_ALLMULTI)) {
|
|
/* Too many to filter perfectly -- accept all multicasts. */
|
|
rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
|
|
mc_filter[1] = mc_filter[0] = 0xffffffff;
|
|
} else {
|
|
struct dev_mc_list *mclist;
|
|
rx_mode = AcceptBroadcast | AcceptMyPhys;
|
|
mc_filter[1] = mc_filter[0] = 0;
|
|
for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
|
|
i++, mclist = mclist->next) {
|
|
int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
|
|
|
|
mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
|
|
rx_mode |= AcceptMulticast;
|
|
}
|
|
}
|
|
|
|
/* We can safely update without stopping the chip. */
|
|
tmp = cp_rx_config | rx_mode;
|
|
if (cp->rx_config != tmp) {
|
|
cpw32_f (RxConfig, tmp);
|
|
cp->rx_config = tmp;
|
|
}
|
|
cpw32_f (MAR0 + 0, mc_filter[0]);
|
|
cpw32_f (MAR0 + 4, mc_filter[1]);
|
|
}
|
|
|
|
static void cp_set_rx_mode (struct net_device *dev)
|
|
{
|
|
unsigned long flags;
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
|
|
spin_lock_irqsave (&cp->lock, flags);
|
|
__cp_set_rx_mode(dev);
|
|
spin_unlock_irqrestore (&cp->lock, flags);
|
|
}
|
|
|
|
static void __cp_get_stats(struct cp_private *cp)
|
|
{
|
|
/* only lower 24 bits valid; write any value to clear */
|
|
cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
|
|
cpw32 (RxMissed, 0);
|
|
}
|
|
|
|
static struct net_device_stats *cp_get_stats(struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
/* The chip only need report frame silently dropped. */
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
if (netif_running(dev) && netif_device_present(dev))
|
|
__cp_get_stats(cp);
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
|
|
return &dev->stats;
|
|
}
|
|
|
|
static void cp_stop_hw (struct cp_private *cp)
|
|
{
|
|
cpw16(IntrStatus, ~(cpr16(IntrStatus)));
|
|
cpw16_f(IntrMask, 0);
|
|
cpw8(Cmd, 0);
|
|
cpw16_f(CpCmd, 0);
|
|
cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
|
|
|
|
cp->rx_tail = 0;
|
|
cp->tx_head = cp->tx_tail = 0;
|
|
}
|
|
|
|
static void cp_reset_hw (struct cp_private *cp)
|
|
{
|
|
unsigned work = 1000;
|
|
|
|
cpw8(Cmd, CmdReset);
|
|
|
|
while (work--) {
|
|
if (!(cpr8(Cmd) & CmdReset))
|
|
return;
|
|
|
|
schedule_timeout_uninterruptible(10);
|
|
}
|
|
|
|
printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
|
|
}
|
|
|
|
static inline void cp_start_hw (struct cp_private *cp)
|
|
{
|
|
cpw16(CpCmd, cp->cpcmd);
|
|
cpw8(Cmd, RxOn | TxOn);
|
|
}
|
|
|
|
static void cp_init_hw (struct cp_private *cp)
|
|
{
|
|
struct net_device *dev = cp->dev;
|
|
dma_addr_t ring_dma;
|
|
|
|
cp_reset_hw(cp);
|
|
|
|
cpw8_f (Cfg9346, Cfg9346_Unlock);
|
|
|
|
/* Restore our idea of the MAC address. */
|
|
cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
|
|
cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
|
|
|
|
cp_start_hw(cp);
|
|
cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
|
|
|
|
__cp_set_rx_mode(dev);
|
|
cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
|
|
|
|
cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
|
|
/* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
|
|
cpw8(Config3, PARMEnable);
|
|
cp->wol_enabled = 0;
|
|
|
|
cpw8(Config5, cpr8(Config5) & PMEStatus);
|
|
|
|
cpw32_f(HiTxRingAddr, 0);
|
|
cpw32_f(HiTxRingAddr + 4, 0);
|
|
|
|
ring_dma = cp->ring_dma;
|
|
cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
|
|
cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
|
|
|
|
ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
|
|
cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
|
|
cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
|
|
|
|
cpw16(MultiIntr, 0);
|
|
|
|
cpw16_f(IntrMask, cp_intr_mask);
|
|
|
|
cpw8_f(Cfg9346, Cfg9346_Lock);
|
|
}
|
|
|
|
static int cp_refill_rx(struct cp_private *cp)
|
|
{
|
|
struct net_device *dev = cp->dev;
|
|
unsigned i;
|
|
|
|
for (i = 0; i < CP_RX_RING_SIZE; i++) {
|
|
struct sk_buff *skb;
|
|
dma_addr_t mapping;
|
|
|
|
skb = netdev_alloc_skb(dev, cp->rx_buf_sz + NET_IP_ALIGN);
|
|
if (!skb)
|
|
goto err_out;
|
|
|
|
skb_reserve(skb, NET_IP_ALIGN);
|
|
|
|
mapping = dma_map_single(&cp->pdev->dev, skb->data,
|
|
cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
|
|
cp->rx_skb[i] = skb;
|
|
|
|
cp->rx_ring[i].opts2 = 0;
|
|
cp->rx_ring[i].addr = cpu_to_le64(mapping);
|
|
if (i == (CP_RX_RING_SIZE - 1))
|
|
cp->rx_ring[i].opts1 =
|
|
cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
|
|
else
|
|
cp->rx_ring[i].opts1 =
|
|
cpu_to_le32(DescOwn | cp->rx_buf_sz);
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
cp_clean_rings(cp);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void cp_init_rings_index (struct cp_private *cp)
|
|
{
|
|
cp->rx_tail = 0;
|
|
cp->tx_head = cp->tx_tail = 0;
|
|
}
|
|
|
|
static int cp_init_rings (struct cp_private *cp)
|
|
{
|
|
memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
|
|
cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
|
|
|
|
cp_init_rings_index(cp);
|
|
|
|
return cp_refill_rx (cp);
|
|
}
|
|
|
|
static int cp_alloc_rings (struct cp_private *cp)
|
|
{
|
|
void *mem;
|
|
|
|
mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
|
|
&cp->ring_dma, GFP_KERNEL);
|
|
if (!mem)
|
|
return -ENOMEM;
|
|
|
|
cp->rx_ring = mem;
|
|
cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
|
|
|
|
return cp_init_rings(cp);
|
|
}
|
|
|
|
static void cp_clean_rings (struct cp_private *cp)
|
|
{
|
|
struct cp_desc *desc;
|
|
unsigned i;
|
|
|
|
for (i = 0; i < CP_RX_RING_SIZE; i++) {
|
|
if (cp->rx_skb[i]) {
|
|
desc = cp->rx_ring + i;
|
|
dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
|
|
cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
|
|
dev_kfree_skb(cp->rx_skb[i]);
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < CP_TX_RING_SIZE; i++) {
|
|
if (cp->tx_skb[i]) {
|
|
struct sk_buff *skb = cp->tx_skb[i];
|
|
|
|
desc = cp->tx_ring + i;
|
|
dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
|
|
le32_to_cpu(desc->opts1) & 0xffff,
|
|
PCI_DMA_TODEVICE);
|
|
if (le32_to_cpu(desc->opts1) & LastFrag)
|
|
dev_kfree_skb(skb);
|
|
cp->dev->stats.tx_dropped++;
|
|
}
|
|
}
|
|
|
|
memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
|
|
memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
|
|
|
|
memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
|
|
memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
|
|
}
|
|
|
|
static void cp_free_rings (struct cp_private *cp)
|
|
{
|
|
cp_clean_rings(cp);
|
|
dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
|
|
cp->ring_dma);
|
|
cp->rx_ring = NULL;
|
|
cp->tx_ring = NULL;
|
|
}
|
|
|
|
static int cp_open (struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
int rc;
|
|
|
|
if (netif_msg_ifup(cp))
|
|
printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
|
|
|
|
rc = cp_alloc_rings(cp);
|
|
if (rc)
|
|
return rc;
|
|
|
|
napi_enable(&cp->napi);
|
|
|
|
cp_init_hw(cp);
|
|
|
|
rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
|
|
if (rc)
|
|
goto err_out_hw;
|
|
|
|
netif_carrier_off(dev);
|
|
mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
|
|
netif_start_queue(dev);
|
|
|
|
return 0;
|
|
|
|
err_out_hw:
|
|
napi_disable(&cp->napi);
|
|
cp_stop_hw(cp);
|
|
cp_free_rings(cp);
|
|
return rc;
|
|
}
|
|
|
|
static int cp_close (struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
napi_disable(&cp->napi);
|
|
|
|
if (netif_msg_ifdown(cp))
|
|
printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
|
|
netif_stop_queue(dev);
|
|
netif_carrier_off(dev);
|
|
|
|
cp_stop_hw(cp);
|
|
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
|
|
free_irq(dev->irq, dev);
|
|
|
|
cp_free_rings(cp);
|
|
return 0;
|
|
}
|
|
|
|
static void cp_tx_timeout(struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned long flags;
|
|
int rc;
|
|
|
|
printk(KERN_WARNING "%s: Transmit timeout, status %2x %4x %4x %4x\n",
|
|
dev->name, cpr8(Cmd), cpr16(CpCmd),
|
|
cpr16(IntrStatus), cpr16(IntrMask));
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
|
|
cp_stop_hw(cp);
|
|
cp_clean_rings(cp);
|
|
rc = cp_init_rings(cp);
|
|
cp_start_hw(cp);
|
|
|
|
netif_wake_queue(dev);
|
|
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
|
|
return;
|
|
}
|
|
|
|
#ifdef BROKEN
|
|
static int cp_change_mtu(struct net_device *dev, int new_mtu)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
int rc;
|
|
unsigned long flags;
|
|
|
|
/* check for invalid MTU, according to hardware limits */
|
|
if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
|
|
return -EINVAL;
|
|
|
|
/* if network interface not up, no need for complexity */
|
|
if (!netif_running(dev)) {
|
|
dev->mtu = new_mtu;
|
|
cp_set_rxbufsize(cp); /* set new rx buf size */
|
|
return 0;
|
|
}
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
|
|
cp_stop_hw(cp); /* stop h/w and free rings */
|
|
cp_clean_rings(cp);
|
|
|
|
dev->mtu = new_mtu;
|
|
cp_set_rxbufsize(cp); /* set new rx buf size */
|
|
|
|
rc = cp_init_rings(cp); /* realloc and restart h/w */
|
|
cp_start_hw(cp);
|
|
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
|
|
return rc;
|
|
}
|
|
#endif /* BROKEN */
|
|
|
|
static const char mii_2_8139_map[8] = {
|
|
BasicModeCtrl,
|
|
BasicModeStatus,
|
|
0,
|
|
0,
|
|
NWayAdvert,
|
|
NWayLPAR,
|
|
NWayExpansion,
|
|
0
|
|
};
|
|
|
|
static int mdio_read(struct net_device *dev, int phy_id, int location)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
|
|
return location < 8 && mii_2_8139_map[location] ?
|
|
readw(cp->regs + mii_2_8139_map[location]) : 0;
|
|
}
|
|
|
|
|
|
static void mdio_write(struct net_device *dev, int phy_id, int location,
|
|
int value)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
|
|
if (location == 0) {
|
|
cpw8(Cfg9346, Cfg9346_Unlock);
|
|
cpw16(BasicModeCtrl, value);
|
|
cpw8(Cfg9346, Cfg9346_Lock);
|
|
} else if (location < 8 && mii_2_8139_map[location])
|
|
cpw16(mii_2_8139_map[location], value);
|
|
}
|
|
|
|
/* Set the ethtool Wake-on-LAN settings */
|
|
static int netdev_set_wol (struct cp_private *cp,
|
|
const struct ethtool_wolinfo *wol)
|
|
{
|
|
u8 options;
|
|
|
|
options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
|
|
/* If WOL is being disabled, no need for complexity */
|
|
if (wol->wolopts) {
|
|
if (wol->wolopts & WAKE_PHY) options |= LinkUp;
|
|
if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
|
|
}
|
|
|
|
cpw8 (Cfg9346, Cfg9346_Unlock);
|
|
cpw8 (Config3, options);
|
|
cpw8 (Cfg9346, Cfg9346_Lock);
|
|
|
|
options = 0; /* Paranoia setting */
|
|
options = cpr8 (Config5) & ~(UWF | MWF | BWF);
|
|
/* If WOL is being disabled, no need for complexity */
|
|
if (wol->wolopts) {
|
|
if (wol->wolopts & WAKE_UCAST) options |= UWF;
|
|
if (wol->wolopts & WAKE_BCAST) options |= BWF;
|
|
if (wol->wolopts & WAKE_MCAST) options |= MWF;
|
|
}
|
|
|
|
cpw8 (Config5, options);
|
|
|
|
cp->wol_enabled = (wol->wolopts) ? 1 : 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Get the ethtool Wake-on-LAN settings */
|
|
static void netdev_get_wol (struct cp_private *cp,
|
|
struct ethtool_wolinfo *wol)
|
|
{
|
|
u8 options;
|
|
|
|
wol->wolopts = 0; /* Start from scratch */
|
|
wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
|
|
WAKE_MCAST | WAKE_UCAST;
|
|
/* We don't need to go on if WOL is disabled */
|
|
if (!cp->wol_enabled) return;
|
|
|
|
options = cpr8 (Config3);
|
|
if (options & LinkUp) wol->wolopts |= WAKE_PHY;
|
|
if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
|
|
|
|
options = 0; /* Paranoia setting */
|
|
options = cpr8 (Config5);
|
|
if (options & UWF) wol->wolopts |= WAKE_UCAST;
|
|
if (options & BWF) wol->wolopts |= WAKE_BCAST;
|
|
if (options & MWF) wol->wolopts |= WAKE_MCAST;
|
|
}
|
|
|
|
static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
|
|
strcpy (info->driver, DRV_NAME);
|
|
strcpy (info->version, DRV_VERSION);
|
|
strcpy (info->bus_info, pci_name(cp->pdev));
|
|
}
|
|
|
|
static int cp_get_regs_len(struct net_device *dev)
|
|
{
|
|
return CP_REGS_SIZE;
|
|
}
|
|
|
|
static int cp_get_sset_count (struct net_device *dev, int sset)
|
|
{
|
|
switch (sset) {
|
|
case ETH_SS_STATS:
|
|
return CP_NUM_STATS;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
int rc;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
rc = mii_ethtool_gset(&cp->mii_if, cmd);
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
int rc;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
rc = mii_ethtool_sset(&cp->mii_if, cmd);
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int cp_nway_reset(struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
return mii_nway_restart(&cp->mii_if);
|
|
}
|
|
|
|
static u32 cp_get_msglevel(struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
return cp->msg_enable;
|
|
}
|
|
|
|
static void cp_set_msglevel(struct net_device *dev, u32 value)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
cp->msg_enable = value;
|
|
}
|
|
|
|
static u32 cp_get_rx_csum(struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
|
|
}
|
|
|
|
static int cp_set_rx_csum(struct net_device *dev, u32 data)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
u16 cmd = cp->cpcmd, newcmd;
|
|
|
|
newcmd = cmd;
|
|
|
|
if (data)
|
|
newcmd |= RxChkSum;
|
|
else
|
|
newcmd &= ~RxChkSum;
|
|
|
|
if (newcmd != cmd) {
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
cp->cpcmd = newcmd;
|
|
cpw16_f(CpCmd, newcmd);
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
|
|
void *p)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
if (regs->len < CP_REGS_SIZE)
|
|
return /* -EINVAL */;
|
|
|
|
regs->version = CP_REGS_VER;
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
}
|
|
|
|
static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave (&cp->lock, flags);
|
|
netdev_get_wol (cp, wol);
|
|
spin_unlock_irqrestore (&cp->lock, flags);
|
|
}
|
|
|
|
static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned long flags;
|
|
int rc;
|
|
|
|
spin_lock_irqsave (&cp->lock, flags);
|
|
rc = netdev_set_wol (cp, wol);
|
|
spin_unlock_irqrestore (&cp->lock, flags);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
|
|
{
|
|
switch (stringset) {
|
|
case ETH_SS_STATS:
|
|
memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
|
|
break;
|
|
default:
|
|
BUG();
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void cp_get_ethtool_stats (struct net_device *dev,
|
|
struct ethtool_stats *estats, u64 *tmp_stats)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
struct cp_dma_stats *nic_stats;
|
|
dma_addr_t dma;
|
|
int i;
|
|
|
|
nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
|
|
&dma, GFP_KERNEL);
|
|
if (!nic_stats)
|
|
return;
|
|
|
|
/* begin NIC statistics dump */
|
|
cpw32(StatsAddr + 4, (u64)dma >> 32);
|
|
cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
|
|
cpr32(StatsAddr);
|
|
|
|
for (i = 0; i < 1000; i++) {
|
|
if ((cpr32(StatsAddr) & DumpStats) == 0)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
cpw32(StatsAddr, 0);
|
|
cpw32(StatsAddr + 4, 0);
|
|
cpr32(StatsAddr);
|
|
|
|
i = 0;
|
|
tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
|
|
tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
|
|
tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
|
|
tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
|
|
tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
|
|
tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
|
|
tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
|
|
tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
|
|
tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
|
|
tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
|
|
tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
|
|
tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
|
|
tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
|
|
tmp_stats[i++] = cp->cp_stats.rx_frags;
|
|
BUG_ON(i != CP_NUM_STATS);
|
|
|
|
dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
|
|
}
|
|
|
|
static const struct ethtool_ops cp_ethtool_ops = {
|
|
.get_drvinfo = cp_get_drvinfo,
|
|
.get_regs_len = cp_get_regs_len,
|
|
.get_sset_count = cp_get_sset_count,
|
|
.get_settings = cp_get_settings,
|
|
.set_settings = cp_set_settings,
|
|
.nway_reset = cp_nway_reset,
|
|
.get_link = ethtool_op_get_link,
|
|
.get_msglevel = cp_get_msglevel,
|
|
.set_msglevel = cp_set_msglevel,
|
|
.get_rx_csum = cp_get_rx_csum,
|
|
.set_rx_csum = cp_set_rx_csum,
|
|
.set_tx_csum = ethtool_op_set_tx_csum, /* local! */
|
|
.set_sg = ethtool_op_set_sg,
|
|
.set_tso = ethtool_op_set_tso,
|
|
.get_regs = cp_get_regs,
|
|
.get_wol = cp_get_wol,
|
|
.set_wol = cp_set_wol,
|
|
.get_strings = cp_get_strings,
|
|
.get_ethtool_stats = cp_get_ethtool_stats,
|
|
.get_eeprom_len = cp_get_eeprom_len,
|
|
.get_eeprom = cp_get_eeprom,
|
|
.set_eeprom = cp_set_eeprom,
|
|
};
|
|
|
|
static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
int rc;
|
|
unsigned long flags;
|
|
|
|
if (!netif_running(dev))
|
|
return -EINVAL;
|
|
|
|
spin_lock_irqsave(&cp->lock, flags);
|
|
rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
|
|
spin_unlock_irqrestore(&cp->lock, flags);
|
|
return rc;
|
|
}
|
|
|
|
/* Serial EEPROM section. */
|
|
|
|
/* EEPROM_Ctrl bits. */
|
|
#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
|
|
#define EE_CS 0x08 /* EEPROM chip select. */
|
|
#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
|
|
#define EE_WRITE_0 0x00
|
|
#define EE_WRITE_1 0x02
|
|
#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
|
|
#define EE_ENB (0x80 | EE_CS)
|
|
|
|
/* Delay between EEPROM clock transitions.
|
|
No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
|
|
*/
|
|
|
|
#define eeprom_delay() readl(ee_addr)
|
|
|
|
/* The EEPROM commands include the alway-set leading bit. */
|
|
#define EE_EXTEND_CMD (4)
|
|
#define EE_WRITE_CMD (5)
|
|
#define EE_READ_CMD (6)
|
|
#define EE_ERASE_CMD (7)
|
|
|
|
#define EE_EWDS_ADDR (0)
|
|
#define EE_WRAL_ADDR (1)
|
|
#define EE_ERAL_ADDR (2)
|
|
#define EE_EWEN_ADDR (3)
|
|
|
|
#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
|
|
|
|
static void eeprom_cmd_start(void __iomem *ee_addr)
|
|
{
|
|
writeb (EE_ENB & ~EE_CS, ee_addr);
|
|
writeb (EE_ENB, ee_addr);
|
|
eeprom_delay ();
|
|
}
|
|
|
|
static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
|
|
{
|
|
int i;
|
|
|
|
/* Shift the command bits out. */
|
|
for (i = cmd_len - 1; i >= 0; i--) {
|
|
int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
|
|
writeb (EE_ENB | dataval, ee_addr);
|
|
eeprom_delay ();
|
|
writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
|
|
eeprom_delay ();
|
|
}
|
|
writeb (EE_ENB, ee_addr);
|
|
eeprom_delay ();
|
|
}
|
|
|
|
static void eeprom_cmd_end(void __iomem *ee_addr)
|
|
{
|
|
writeb (~EE_CS, ee_addr);
|
|
eeprom_delay ();
|
|
}
|
|
|
|
static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
|
|
int addr_len)
|
|
{
|
|
int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
|
|
|
|
eeprom_cmd_start(ee_addr);
|
|
eeprom_cmd(ee_addr, cmd, 3 + addr_len);
|
|
eeprom_cmd_end(ee_addr);
|
|
}
|
|
|
|
static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
|
|
{
|
|
int i;
|
|
u16 retval = 0;
|
|
void __iomem *ee_addr = ioaddr + Cfg9346;
|
|
int read_cmd = location | (EE_READ_CMD << addr_len);
|
|
|
|
eeprom_cmd_start(ee_addr);
|
|
eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
|
|
|
|
for (i = 16; i > 0; i--) {
|
|
writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
|
|
eeprom_delay ();
|
|
retval =
|
|
(retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
|
|
0);
|
|
writeb (EE_ENB, ee_addr);
|
|
eeprom_delay ();
|
|
}
|
|
|
|
eeprom_cmd_end(ee_addr);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
|
|
int addr_len)
|
|
{
|
|
int i;
|
|
void __iomem *ee_addr = ioaddr + Cfg9346;
|
|
int write_cmd = location | (EE_WRITE_CMD << addr_len);
|
|
|
|
eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
|
|
|
|
eeprom_cmd_start(ee_addr);
|
|
eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
|
|
eeprom_cmd(ee_addr, val, 16);
|
|
eeprom_cmd_end(ee_addr);
|
|
|
|
eeprom_cmd_start(ee_addr);
|
|
for (i = 0; i < 20000; i++)
|
|
if (readb(ee_addr) & EE_DATA_READ)
|
|
break;
|
|
eeprom_cmd_end(ee_addr);
|
|
|
|
eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
|
|
}
|
|
|
|
static int cp_get_eeprom_len(struct net_device *dev)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
int size;
|
|
|
|
spin_lock_irq(&cp->lock);
|
|
size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
|
|
spin_unlock_irq(&cp->lock);
|
|
|
|
return size;
|
|
}
|
|
|
|
static int cp_get_eeprom(struct net_device *dev,
|
|
struct ethtool_eeprom *eeprom, u8 *data)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned int addr_len;
|
|
u16 val;
|
|
u32 offset = eeprom->offset >> 1;
|
|
u32 len = eeprom->len;
|
|
u32 i = 0;
|
|
|
|
eeprom->magic = CP_EEPROM_MAGIC;
|
|
|
|
spin_lock_irq(&cp->lock);
|
|
|
|
addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
|
|
|
|
if (eeprom->offset & 1) {
|
|
val = read_eeprom(cp->regs, offset, addr_len);
|
|
data[i++] = (u8)(val >> 8);
|
|
offset++;
|
|
}
|
|
|
|
while (i < len - 1) {
|
|
val = read_eeprom(cp->regs, offset, addr_len);
|
|
data[i++] = (u8)val;
|
|
data[i++] = (u8)(val >> 8);
|
|
offset++;
|
|
}
|
|
|
|
if (i < len) {
|
|
val = read_eeprom(cp->regs, offset, addr_len);
|
|
data[i] = (u8)val;
|
|
}
|
|
|
|
spin_unlock_irq(&cp->lock);
|
|
return 0;
|
|
}
|
|
|
|
static int cp_set_eeprom(struct net_device *dev,
|
|
struct ethtool_eeprom *eeprom, u8 *data)
|
|
{
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned int addr_len;
|
|
u16 val;
|
|
u32 offset = eeprom->offset >> 1;
|
|
u32 len = eeprom->len;
|
|
u32 i = 0;
|
|
|
|
if (eeprom->magic != CP_EEPROM_MAGIC)
|
|
return -EINVAL;
|
|
|
|
spin_lock_irq(&cp->lock);
|
|
|
|
addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
|
|
|
|
if (eeprom->offset & 1) {
|
|
val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
|
|
val |= (u16)data[i++] << 8;
|
|
write_eeprom(cp->regs, offset, val, addr_len);
|
|
offset++;
|
|
}
|
|
|
|
while (i < len - 1) {
|
|
val = (u16)data[i++];
|
|
val |= (u16)data[i++] << 8;
|
|
write_eeprom(cp->regs, offset, val, addr_len);
|
|
offset++;
|
|
}
|
|
|
|
if (i < len) {
|
|
val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
|
|
val |= (u16)data[i];
|
|
write_eeprom(cp->regs, offset, val, addr_len);
|
|
}
|
|
|
|
spin_unlock_irq(&cp->lock);
|
|
return 0;
|
|
}
|
|
|
|
/* Put the board into D3cold state and wait for WakeUp signal */
|
|
static void cp_set_d3_state (struct cp_private *cp)
|
|
{
|
|
pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
|
|
pci_set_power_state (cp->pdev, PCI_D3hot);
|
|
}
|
|
|
|
static const struct net_device_ops cp_netdev_ops = {
|
|
.ndo_open = cp_open,
|
|
.ndo_stop = cp_close,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
.ndo_set_multicast_list = cp_set_rx_mode,
|
|
.ndo_get_stats = cp_get_stats,
|
|
.ndo_do_ioctl = cp_ioctl,
|
|
.ndo_start_xmit = cp_start_xmit,
|
|
.ndo_tx_timeout = cp_tx_timeout,
|
|
#if CP_VLAN_TAG_USED
|
|
.ndo_vlan_rx_register = cp_vlan_rx_register,
|
|
#endif
|
|
#ifdef BROKEN
|
|
.ndo_change_mtu = cp_change_mtu,
|
|
#endif
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
.ndo_poll_controller = cp_poll_controller,
|
|
#endif
|
|
};
|
|
|
|
static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
struct net_device *dev;
|
|
struct cp_private *cp;
|
|
int rc;
|
|
void __iomem *regs;
|
|
resource_size_t pciaddr;
|
|
unsigned int addr_len, i, pci_using_dac;
|
|
|
|
#ifndef MODULE
|
|
static int version_printed;
|
|
if (version_printed++ == 0)
|
|
printk("%s", version);
|
|
#endif
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
|
|
pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
|
|
dev_info(&pdev->dev,
|
|
"This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
|
|
pdev->vendor, pdev->device, pdev->revision);
|
|
return -ENODEV;
|
|
}
|
|
|
|
dev = alloc_etherdev(sizeof(struct cp_private));
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
cp = netdev_priv(dev);
|
|
cp->pdev = pdev;
|
|
cp->dev = dev;
|
|
cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
|
|
spin_lock_init (&cp->lock);
|
|
cp->mii_if.dev = dev;
|
|
cp->mii_if.mdio_read = mdio_read;
|
|
cp->mii_if.mdio_write = mdio_write;
|
|
cp->mii_if.phy_id = CP_INTERNAL_PHY;
|
|
cp->mii_if.phy_id_mask = 0x1f;
|
|
cp->mii_if.reg_num_mask = 0x1f;
|
|
cp_set_rxbufsize(cp);
|
|
|
|
rc = pci_enable_device(pdev);
|
|
if (rc)
|
|
goto err_out_free;
|
|
|
|
rc = pci_set_mwi(pdev);
|
|
if (rc)
|
|
goto err_out_disable;
|
|
|
|
rc = pci_request_regions(pdev, DRV_NAME);
|
|
if (rc)
|
|
goto err_out_mwi;
|
|
|
|
pciaddr = pci_resource_start(pdev, 1);
|
|
if (!pciaddr) {
|
|
rc = -EIO;
|
|
dev_err(&pdev->dev, "no MMIO resource\n");
|
|
goto err_out_res;
|
|
}
|
|
if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
|
|
rc = -EIO;
|
|
dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
|
|
(unsigned long long)pci_resource_len(pdev, 1));
|
|
goto err_out_res;
|
|
}
|
|
|
|
/* Configure DMA attributes. */
|
|
if ((sizeof(dma_addr_t) > 4) &&
|
|
!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
|
|
!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
|
|
pci_using_dac = 1;
|
|
} else {
|
|
pci_using_dac = 0;
|
|
|
|
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
|
if (rc) {
|
|
dev_err(&pdev->dev,
|
|
"No usable DMA configuration, aborting.\n");
|
|
goto err_out_res;
|
|
}
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
|
if (rc) {
|
|
dev_err(&pdev->dev,
|
|
"No usable consistent DMA configuration, "
|
|
"aborting.\n");
|
|
goto err_out_res;
|
|
}
|
|
}
|
|
|
|
cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
|
|
PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
|
|
|
|
regs = ioremap(pciaddr, CP_REGS_SIZE);
|
|
if (!regs) {
|
|
rc = -EIO;
|
|
dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
|
|
(unsigned long long)pci_resource_len(pdev, 1),
|
|
(unsigned long long)pciaddr);
|
|
goto err_out_res;
|
|
}
|
|
dev->base_addr = (unsigned long) regs;
|
|
cp->regs = regs;
|
|
|
|
cp_stop_hw(cp);
|
|
|
|
/* read MAC address from EEPROM */
|
|
addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
|
|
for (i = 0; i < 3; i++)
|
|
((__le16 *) (dev->dev_addr))[i] =
|
|
cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
|
|
memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
|
|
|
|
dev->netdev_ops = &cp_netdev_ops;
|
|
netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
|
|
dev->ethtool_ops = &cp_ethtool_ops;
|
|
dev->watchdog_timeo = TX_TIMEOUT;
|
|
|
|
#if CP_VLAN_TAG_USED
|
|
dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
|
|
#endif
|
|
|
|
if (pci_using_dac)
|
|
dev->features |= NETIF_F_HIGHDMA;
|
|
|
|
#if 0 /* disabled by default until verified */
|
|
dev->features |= NETIF_F_TSO;
|
|
#endif
|
|
|
|
dev->irq = pdev->irq;
|
|
|
|
rc = register_netdev(dev);
|
|
if (rc)
|
|
goto err_out_iomap;
|
|
|
|
printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
|
|
"%pM, IRQ %d\n",
|
|
dev->name,
|
|
dev->base_addr,
|
|
dev->dev_addr,
|
|
dev->irq);
|
|
|
|
pci_set_drvdata(pdev, dev);
|
|
|
|
/* enable busmastering and memory-write-invalidate */
|
|
pci_set_master(pdev);
|
|
|
|
if (cp->wol_enabled)
|
|
cp_set_d3_state (cp);
|
|
|
|
return 0;
|
|
|
|
err_out_iomap:
|
|
iounmap(regs);
|
|
err_out_res:
|
|
pci_release_regions(pdev);
|
|
err_out_mwi:
|
|
pci_clear_mwi(pdev);
|
|
err_out_disable:
|
|
pci_disable_device(pdev);
|
|
err_out_free:
|
|
free_netdev(dev);
|
|
return rc;
|
|
}
|
|
|
|
static void cp_remove_one (struct pci_dev *pdev)
|
|
{
|
|
struct net_device *dev = pci_get_drvdata(pdev);
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
|
|
unregister_netdev(dev);
|
|
iounmap(cp->regs);
|
|
if (cp->wol_enabled)
|
|
pci_set_power_state (pdev, PCI_D0);
|
|
pci_release_regions(pdev);
|
|
pci_clear_mwi(pdev);
|
|
pci_disable_device(pdev);
|
|
pci_set_drvdata(pdev, NULL);
|
|
free_netdev(dev);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
|
|
{
|
|
struct net_device *dev = pci_get_drvdata(pdev);
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
if (!netif_running(dev))
|
|
return 0;
|
|
|
|
netif_device_detach (dev);
|
|
netif_stop_queue (dev);
|
|
|
|
spin_lock_irqsave (&cp->lock, flags);
|
|
|
|
/* Disable Rx and Tx */
|
|
cpw16 (IntrMask, 0);
|
|
cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
|
|
|
|
spin_unlock_irqrestore (&cp->lock, flags);
|
|
|
|
pci_save_state(pdev);
|
|
pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
|
|
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cp_resume (struct pci_dev *pdev)
|
|
{
|
|
struct net_device *dev = pci_get_drvdata (pdev);
|
|
struct cp_private *cp = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
if (!netif_running(dev))
|
|
return 0;
|
|
|
|
netif_device_attach (dev);
|
|
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
pci_enable_wake(pdev, PCI_D0, 0);
|
|
|
|
/* FIXME: sh*t may happen if the Rx ring buffer is depleted */
|
|
cp_init_rings_index (cp);
|
|
cp_init_hw (cp);
|
|
netif_start_queue (dev);
|
|
|
|
spin_lock_irqsave (&cp->lock, flags);
|
|
|
|
mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
|
|
|
|
spin_unlock_irqrestore (&cp->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct pci_driver cp_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = cp_pci_tbl,
|
|
.probe = cp_init_one,
|
|
.remove = cp_remove_one,
|
|
#ifdef CONFIG_PM
|
|
.resume = cp_resume,
|
|
.suspend = cp_suspend,
|
|
#endif
|
|
};
|
|
|
|
static int __init cp_init (void)
|
|
{
|
|
#ifdef MODULE
|
|
printk("%s", version);
|
|
#endif
|
|
return pci_register_driver(&cp_driver);
|
|
}
|
|
|
|
static void __exit cp_exit (void)
|
|
{
|
|
pci_unregister_driver (&cp_driver);
|
|
}
|
|
|
|
module_init(cp_init);
|
|
module_exit(cp_exit);
|