![David S. Miller](/assets/img/avatar_default.png)
This is the long overdue conversion of sparc64 over to the generic IRQ layer. The kernel image is slightly larger, but the BSS is ~60K smaller due to the reduced size of struct ino_bucket. A lot of IRQ implementation details, including ino_bucket, were moved out of asm-sparc64/irq.h and are now private to arch/sparc64/kernel/irq.c, and most of the code in irq.c totally disappeared. One thing that's different at the moment is IRQ distribution, we do it at enable_irq() time. If the cpu mask is ALL then we round-robin using a global rotating cpu counter, else we pick the first cpu in the mask to support single cpu targetting. This is similar to what powerpc's XICS IRQ support code does. This works fine on my UP SB1000, and the SMP build goes fine and runs on that machine, but lots of testing on different setups is needed. Signed-off-by: David S. Miller <davem@davemloft.net>
835 lines
20 KiB
C
835 lines
20 KiB
C
/* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
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* irq.c: UltraSparc IRQ handling/init/registry.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/sbus.h>
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#include <asm/iommu.h>
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#include <asm/upa.h>
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#include <asm/oplib.h>
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#include <asm/timer.h>
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#include <asm/smp.h>
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#include <asm/starfire.h>
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#include <asm/uaccess.h>
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#include <asm/cache.h>
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#include <asm/cpudata.h>
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#include <asm/auxio.h>
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#include <asm/head.h>
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/* UPA nodes send interrupt packet to UltraSparc with first data reg
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* value low 5 (7 on Starfire) bits holding the IRQ identifier being
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* delivered. We must translate this into a non-vector IRQ so we can
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* set the softint on this cpu.
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*
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* To make processing these packets efficient and race free we use
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* an array of irq buckets below. The interrupt vector handler in
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* entry.S feeds incoming packets into per-cpu pil-indexed lists.
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* The IVEC handler does not need to act atomically, the PIL dispatch
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* code uses CAS to get an atomic snapshot of the list and clear it
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* at the same time.
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*
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* If you make changes to ino_bucket, please update hand coded assembler
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* of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
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*/
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struct ino_bucket {
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/* Next handler in per-CPU IRQ worklist. We know that
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* bucket pointers have the high 32-bits clear, so to
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* save space we only store the bits we need.
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*/
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/*0x00*/unsigned int irq_chain;
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/* Virtual interrupt number assigned to this INO. */
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/*0x04*/unsigned int virt_irq;
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};
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#define NUM_IVECS (IMAP_INR + 1)
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struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
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#define __irq_ino(irq) \
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(((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
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#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
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#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
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/* This has to be in the main kernel image, it cannot be
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* turned into per-cpu data. The reason is that the main
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* kernel image is locked into the TLB and this structure
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* is accessed from the vectored interrupt trap handler. If
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* access to this structure takes a TLB miss it could cause
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* the 5-level sparc v9 trap stack to overflow.
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*/
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#define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
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static unsigned int virt_to_real_irq_table[NR_IRQS];
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static unsigned char virt_irq_cur = 1;
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static unsigned char virt_irq_alloc(unsigned int real_irq)
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{
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unsigned char ent;
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BUILD_BUG_ON(NR_IRQS >= 256);
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ent = virt_irq_cur;
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if (ent >= NR_IRQS) {
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printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
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return 0;
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}
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virt_irq_cur = ent + 1;
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virt_to_real_irq_table[ent] = real_irq;
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return ent;
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}
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#if 0 /* Currently unused. */
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static unsigned char real_to_virt_irq(unsigned int real_irq)
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{
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struct ino_bucket *bucket = __bucket(real_irq);
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return bucket->virt_irq;
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}
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#endif
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static unsigned int virt_to_real_irq(unsigned char virt_irq)
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{
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return virt_to_real_irq_table[virt_irq];
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}
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/*
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* /proc/interrupts printing:
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*/
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int show_interrupts(struct seq_file *p, void *v)
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{
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int i = *(loff_t *) v, j;
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struct irqaction * action;
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unsigned long flags;
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if (i == 0) {
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seq_printf(p, " ");
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for_each_online_cpu(j)
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seq_printf(p, "CPU%d ",j);
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seq_putc(p, '\n');
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}
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if (i < NR_IRQS) {
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spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (!action)
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goto skip;
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seq_printf(p, "%3d: ",i);
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#ifndef CONFIG_SMP
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seq_printf(p, "%10u ", kstat_irqs(i));
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#else
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
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#endif
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seq_printf(p, " %9s", irq_desc[i].handler->typename);
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seq_printf(p, " %s", action->name);
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for (action=action->next; action; action = action->next)
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seq_printf(p, ", %s", action->name);
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seq_putc(p, '\n');
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skip:
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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}
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return 0;
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}
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extern unsigned long real_hard_smp_processor_id(void);
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static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
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{
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unsigned int tid;
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if (this_is_starfire) {
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tid = starfire_translate(imap, cpuid);
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tid <<= IMAP_TID_SHIFT;
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tid &= IMAP_TID_UPA;
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} else {
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if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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unsigned long ver;
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__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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if ((ver >> 32UL) == __JALAPENO_ID ||
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(ver >> 32UL) == __SERRANO_ID) {
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tid = cpuid << IMAP_TID_SHIFT;
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tid &= IMAP_TID_JBUS;
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} else {
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unsigned int a = cpuid & 0x1f;
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unsigned int n = (cpuid >> 5) & 0x1f;
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tid = ((a << IMAP_AID_SHIFT) |
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(n << IMAP_NID_SHIFT));
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tid &= (IMAP_AID_SAFARI |
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IMAP_NID_SAFARI);;
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}
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} else {
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tid = cpuid << IMAP_TID_SHIFT;
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tid &= IMAP_TID_UPA;
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}
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}
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return tid;
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}
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struct irq_handler_data {
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unsigned long iclr;
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unsigned long imap;
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void (*pre_handler)(unsigned int, void *, void *);
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void *pre_handler_arg1;
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void *pre_handler_arg2;
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};
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static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq)
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{
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unsigned int real_irq = virt_to_real_irq(virt_irq);
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struct ino_bucket *bucket = NULL;
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if (likely(real_irq))
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bucket = __bucket(real_irq);
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return bucket;
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}
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#ifdef CONFIG_SMP
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static int irq_choose_cpu(unsigned int virt_irq)
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{
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cpumask_t mask = irq_affinity[virt_irq];
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int cpuid;
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if (cpus_equal(mask, CPU_MASK_ALL)) {
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static int irq_rover;
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static DEFINE_SPINLOCK(irq_rover_lock);
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unsigned long flags;
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/* Round-robin distribution... */
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do_round_robin:
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spin_lock_irqsave(&irq_rover_lock, flags);
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while (!cpu_online(irq_rover)) {
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if (++irq_rover >= NR_CPUS)
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irq_rover = 0;
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}
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cpuid = irq_rover;
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do {
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if (++irq_rover >= NR_CPUS)
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irq_rover = 0;
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} while (!cpu_online(irq_rover));
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spin_unlock_irqrestore(&irq_rover_lock, flags);
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} else {
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cpumask_t tmp;
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cpus_and(tmp, cpu_online_map, mask);
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if (cpus_empty(tmp))
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goto do_round_robin;
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cpuid = first_cpu(tmp);
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}
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return cpuid;
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}
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#else
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static int irq_choose_cpu(unsigned int virt_irq)
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{
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return real_hard_smp_processor_id();
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}
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#endif
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static void sun4u_irq_enable(unsigned int virt_irq)
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{
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irq_desc_t *desc = irq_desc + virt_irq;
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struct irq_handler_data *data = desc->handler_data;
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if (likely(data)) {
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unsigned long cpuid, imap;
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unsigned int tid;
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cpuid = irq_choose_cpu(virt_irq);
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imap = data->imap;
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tid = sun4u_compute_tid(imap, cpuid);
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upa_writel(tid | IMAP_VALID, imap);
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}
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}
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static void sun4u_irq_disable(unsigned int virt_irq)
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{
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irq_desc_t *desc = irq_desc + virt_irq;
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struct irq_handler_data *data = desc->handler_data;
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if (likely(data)) {
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unsigned long imap = data->imap;
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u32 tmp = upa_readl(imap);
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tmp &= ~IMAP_VALID;
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upa_writel(tmp, imap);
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}
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}
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static void sun4u_irq_end(unsigned int virt_irq)
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{
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irq_desc_t *desc = irq_desc + virt_irq;
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struct irq_handler_data *data = desc->handler_data;
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if (likely(data))
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upa_writel(ICLR_IDLE, data->iclr);
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}
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static void sun4v_irq_enable(unsigned int virt_irq)
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{
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struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
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unsigned int ino = bucket - &ivector_table[0];
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if (likely(bucket)) {
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unsigned long cpuid;
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int err;
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cpuid = irq_choose_cpu(virt_irq);
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err = sun4v_intr_settarget(ino, cpuid);
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if (err != HV_EOK)
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printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
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ino, cpuid, err);
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err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
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if (err != HV_EOK)
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printk("sun4v_intr_setenabled(%x): err(%d)\n",
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ino, err);
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}
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}
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static void sun4v_irq_disable(unsigned int virt_irq)
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{
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struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
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unsigned int ino = bucket - &ivector_table[0];
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if (likely(bucket)) {
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int err;
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err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
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if (err != HV_EOK)
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printk("sun4v_intr_setenabled(%x): "
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"err(%d)\n", ino, err);
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}
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}
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static void sun4v_irq_end(unsigned int virt_irq)
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{
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struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
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unsigned int ino = bucket - &ivector_table[0];
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if (likely(bucket)) {
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int err;
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err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
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if (err != HV_EOK)
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printk("sun4v_intr_setstate(%x): "
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"err(%d)\n", ino, err);
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}
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}
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static void run_pre_handler(unsigned int virt_irq)
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{
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struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
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irq_desc_t *desc = irq_desc + virt_irq;
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struct irq_handler_data *data = desc->handler_data;
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if (likely(data->pre_handler)) {
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data->pre_handler(__irq_ino(__irq(bucket)),
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data->pre_handler_arg1,
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data->pre_handler_arg2);
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}
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}
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static struct hw_interrupt_type sun4u_irq = {
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.typename = "sun4u",
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.enable = sun4u_irq_enable,
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.disable = sun4u_irq_disable,
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.end = sun4u_irq_end,
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};
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static struct hw_interrupt_type sun4u_irq_ack = {
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.typename = "sun4u+ack",
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.enable = sun4u_irq_enable,
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.disable = sun4u_irq_disable,
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.ack = run_pre_handler,
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.end = sun4u_irq_end,
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};
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static struct hw_interrupt_type sun4v_irq = {
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.typename = "sun4v",
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.enable = sun4v_irq_enable,
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.disable = sun4v_irq_disable,
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.end = sun4v_irq_end,
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};
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static struct hw_interrupt_type sun4v_irq_ack = {
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.typename = "sun4v+ack",
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.enable = sun4v_irq_enable,
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.disable = sun4v_irq_disable,
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.ack = run_pre_handler,
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.end = sun4v_irq_end,
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};
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void irq_install_pre_handler(int virt_irq,
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void (*func)(unsigned int, void *, void *),
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void *arg1, void *arg2)
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{
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irq_desc_t *desc = irq_desc + virt_irq;
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struct irq_handler_data *data = desc->handler_data;
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data->pre_handler = func;
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data->pre_handler_arg1 = arg1;
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data->pre_handler_arg2 = arg2;
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desc->handler = (desc->handler == &sun4u_irq ?
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&sun4u_irq_ack : &sun4v_irq_ack);
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}
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unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
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{
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struct ino_bucket *bucket;
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struct irq_handler_data *data;
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irq_desc_t *desc;
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int ino;
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BUG_ON(tlb_type == hypervisor);
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ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
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bucket = &ivector_table[ino];
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if (!bucket->virt_irq) {
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bucket->virt_irq = virt_irq_alloc(__irq(bucket));
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irq_desc[bucket->virt_irq].handler = &sun4u_irq;
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}
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desc = irq_desc + bucket->virt_irq;
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if (unlikely(desc->handler_data))
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goto out;
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data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
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if (unlikely(!data)) {
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prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
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prom_halt();
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}
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desc->handler_data = data;
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data->imap = imap;
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data->iclr = iclr;
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out:
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return bucket->virt_irq;
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}
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unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
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{
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struct ino_bucket *bucket;
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struct irq_handler_data *data;
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unsigned long sysino;
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irq_desc_t *desc;
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BUG_ON(tlb_type != hypervisor);
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sysino = sun4v_devino_to_sysino(devhandle, devino);
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bucket = &ivector_table[sysino];
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if (!bucket->virt_irq) {
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bucket->virt_irq = virt_irq_alloc(__irq(bucket));
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irq_desc[bucket->virt_irq].handler = &sun4v_irq;
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}
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desc = irq_desc + bucket->virt_irq;
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if (unlikely(desc->handler_data))
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goto out;
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data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
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if (unlikely(!data)) {
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prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
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prom_halt();
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}
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desc->handler_data = data;
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/* Catch accidental accesses to these things. IMAP/ICLR handling
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* is done by hypervisor calls on sun4v platforms, not by direct
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* register accesses.
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*/
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data->imap = ~0UL;
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data->iclr = ~0UL;
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out:
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return bucket->virt_irq;
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}
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void hw_resend_irq(struct hw_interrupt_type *handler, unsigned int virt_irq)
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{
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struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
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unsigned long pstate;
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unsigned int *ent;
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__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
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__asm__ __volatile__("wrpr %0, %1, %%pstate"
|
|
: : "r" (pstate), "i" (PSTATE_IE));
|
|
ent = irq_work(smp_processor_id());
|
|
bucket->irq_chain = *ent;
|
|
*ent = __irq(bucket);
|
|
set_softint(1 << PIL_DEVICE_IRQ);
|
|
__asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
|
|
}
|
|
|
|
void ack_bad_irq(unsigned int virt_irq)
|
|
{
|
|
struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
|
|
unsigned int ino = 0xdeadbeef;
|
|
|
|
if (bucket)
|
|
ino = bucket - &ivector_table[0];
|
|
|
|
printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
|
|
ino, virt_irq);
|
|
}
|
|
|
|
#ifndef CONFIG_SMP
|
|
extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
|
|
|
|
void timer_irq(int irq, struct pt_regs *regs)
|
|
{
|
|
unsigned long clr_mask = 1 << irq;
|
|
unsigned long tick_mask = tick_ops->softint_mask;
|
|
|
|
if (get_softint() & tick_mask) {
|
|
irq = 0;
|
|
clr_mask = tick_mask;
|
|
}
|
|
clear_softint(clr_mask);
|
|
|
|
irq_enter();
|
|
|
|
kstat_this_cpu.irqs[0]++;
|
|
timer_interrupt(irq, NULL, regs);
|
|
|
|
irq_exit();
|
|
}
|
|
#endif
|
|
|
|
void handler_irq(int irq, struct pt_regs *regs)
|
|
{
|
|
struct ino_bucket *bucket;
|
|
|
|
clear_softint(1 << irq);
|
|
|
|
irq_enter();
|
|
|
|
/* Sliiiick... */
|
|
bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0));
|
|
while (bucket) {
|
|
struct ino_bucket *next = __bucket(bucket->irq_chain);
|
|
|
|
bucket->irq_chain = 0;
|
|
__do_IRQ(bucket->virt_irq, regs);
|
|
|
|
bucket = next;
|
|
}
|
|
|
|
irq_exit();
|
|
}
|
|
|
|
#ifdef CONFIG_BLK_DEV_FD
|
|
extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);
|
|
|
|
/* XXX No easy way to include asm/floppy.h XXX */
|
|
extern unsigned char *pdma_vaddr;
|
|
extern unsigned long pdma_size;
|
|
extern volatile int doing_pdma;
|
|
extern unsigned long fdc_status;
|
|
|
|
irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
|
|
{
|
|
if (likely(doing_pdma)) {
|
|
void __iomem *stat = (void __iomem *) fdc_status;
|
|
unsigned char *vaddr = pdma_vaddr;
|
|
unsigned long size = pdma_size;
|
|
u8 val;
|
|
|
|
while (size) {
|
|
val = readb(stat);
|
|
if (unlikely(!(val & 0x80))) {
|
|
pdma_vaddr = vaddr;
|
|
pdma_size = size;
|
|
return IRQ_HANDLED;
|
|
}
|
|
if (unlikely(!(val & 0x20))) {
|
|
pdma_vaddr = vaddr;
|
|
pdma_size = size;
|
|
doing_pdma = 0;
|
|
goto main_interrupt;
|
|
}
|
|
if (val & 0x40) {
|
|
/* read */
|
|
*vaddr++ = readb(stat + 1);
|
|
} else {
|
|
unsigned char data = *vaddr++;
|
|
|
|
/* write */
|
|
writeb(data, stat + 1);
|
|
}
|
|
size--;
|
|
}
|
|
|
|
pdma_vaddr = vaddr;
|
|
pdma_size = size;
|
|
|
|
/* Send Terminal Count pulse to floppy controller. */
|
|
val = readb(auxio_register);
|
|
val |= AUXIO_AUX1_FTCNT;
|
|
writeb(val, auxio_register);
|
|
val &= ~AUXIO_AUX1_FTCNT;
|
|
writeb(val, auxio_register);
|
|
|
|
doing_pdma = 0;
|
|
}
|
|
|
|
main_interrupt:
|
|
return floppy_interrupt(irq, dev_cookie, regs);
|
|
}
|
|
EXPORT_SYMBOL(sparc_floppy_irq);
|
|
#endif
|
|
|
|
struct sun5_timer {
|
|
u64 count0;
|
|
u64 limit0;
|
|
u64 count1;
|
|
u64 limit1;
|
|
};
|
|
|
|
static struct sun5_timer *prom_timers;
|
|
static u64 prom_limit0, prom_limit1;
|
|
|
|
static void map_prom_timers(void)
|
|
{
|
|
unsigned int addr[3];
|
|
int tnode, err;
|
|
|
|
/* PROM timer node hangs out in the top level of device siblings... */
|
|
tnode = prom_finddevice("/counter-timer");
|
|
|
|
/* Assume if node is not present, PROM uses different tick mechanism
|
|
* which we should not care about.
|
|
*/
|
|
if (tnode == 0 || tnode == -1) {
|
|
prom_timers = (struct sun5_timer *) 0;
|
|
return;
|
|
}
|
|
|
|
/* If PROM is really using this, it must be mapped by him. */
|
|
err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
|
|
if (err == -1) {
|
|
prom_printf("PROM does not have timer mapped, trying to continue.\n");
|
|
prom_timers = (struct sun5_timer *) 0;
|
|
return;
|
|
}
|
|
prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
|
|
}
|
|
|
|
static void kill_prom_timer(void)
|
|
{
|
|
if (!prom_timers)
|
|
return;
|
|
|
|
/* Save them away for later. */
|
|
prom_limit0 = prom_timers->limit0;
|
|
prom_limit1 = prom_timers->limit1;
|
|
|
|
/* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
|
|
* We turn both off here just to be paranoid.
|
|
*/
|
|
prom_timers->limit0 = 0;
|
|
prom_timers->limit1 = 0;
|
|
|
|
/* Wheee, eat the interrupt packet too... */
|
|
__asm__ __volatile__(
|
|
" mov 0x40, %%g2\n"
|
|
" ldxa [%%g0] %0, %%g1\n"
|
|
" ldxa [%%g2] %1, %%g1\n"
|
|
" stxa %%g0, [%%g0] %0\n"
|
|
" membar #Sync\n"
|
|
: /* no outputs */
|
|
: "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
|
|
: "g1", "g2");
|
|
}
|
|
|
|
void init_irqwork_curcpu(void)
|
|
{
|
|
int cpu = hard_smp_processor_id();
|
|
|
|
trap_block[cpu].irq_worklist = 0;
|
|
}
|
|
|
|
static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
|
|
{
|
|
unsigned long num_entries = 128;
|
|
unsigned long status;
|
|
|
|
status = sun4v_cpu_qconf(type, paddr, num_entries);
|
|
if (status != HV_EOK) {
|
|
prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
|
|
"err %lu\n", type, paddr, num_entries, status);
|
|
prom_halt();
|
|
}
|
|
}
|
|
|
|
static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
|
|
{
|
|
struct trap_per_cpu *tb = &trap_block[this_cpu];
|
|
|
|
register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
|
|
register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
|
|
register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
|
|
register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
|
|
}
|
|
|
|
static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
|
|
{
|
|
void *page;
|
|
|
|
if (use_bootmem)
|
|
page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
else
|
|
page = (void *) get_zeroed_page(GFP_ATOMIC);
|
|
|
|
if (!page) {
|
|
prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
*pa_ptr = __pa(page);
|
|
}
|
|
|
|
static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
|
|
{
|
|
void *page;
|
|
|
|
if (use_bootmem)
|
|
page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
else
|
|
page = (void *) get_zeroed_page(GFP_ATOMIC);
|
|
|
|
if (!page) {
|
|
prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
*pa_ptr = __pa(page);
|
|
}
|
|
|
|
static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
void *page;
|
|
|
|
BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
|
|
|
|
if (use_bootmem)
|
|
page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
else
|
|
page = (void *) get_zeroed_page(GFP_ATOMIC);
|
|
|
|
if (!page) {
|
|
prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
tb->cpu_mondo_block_pa = __pa(page);
|
|
tb->cpu_list_pa = __pa(page + 64);
|
|
#endif
|
|
}
|
|
|
|
/* Allocate and register the mondo and error queues for this cpu. */
|
|
void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
|
|
{
|
|
struct trap_per_cpu *tb = &trap_block[cpu];
|
|
|
|
if (alloc) {
|
|
alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
|
|
alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
|
|
alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
|
|
alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
|
|
alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
|
|
alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
|
|
|
|
init_cpu_send_mondo_info(tb, use_bootmem);
|
|
}
|
|
|
|
if (load) {
|
|
if (cpu != hard_smp_processor_id()) {
|
|
prom_printf("SUN4V: init mondo on cpu %d not %d\n",
|
|
cpu, hard_smp_processor_id());
|
|
prom_halt();
|
|
}
|
|
sun4v_register_mondo_queues(cpu);
|
|
}
|
|
}
|
|
|
|
static struct irqaction timer_irq_action = {
|
|
.name = "timer",
|
|
};
|
|
|
|
/* Only invoked on boot processor. */
|
|
void __init init_IRQ(void)
|
|
{
|
|
map_prom_timers();
|
|
kill_prom_timer();
|
|
memset(&ivector_table[0], 0, sizeof(ivector_table));
|
|
|
|
if (tlb_type == hypervisor)
|
|
sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
|
|
|
|
/* We need to clear any IRQ's pending in the soft interrupt
|
|
* registers, a spurious one could be left around from the
|
|
* PROM timer which we just disabled.
|
|
*/
|
|
clear_softint(get_softint());
|
|
|
|
/* Now that ivector table is initialized, it is safe
|
|
* to receive IRQ vector traps. We will normally take
|
|
* one or two right now, in case some device PROM used
|
|
* to boot us wants to speak to us. We just ignore them.
|
|
*/
|
|
__asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
|
|
"or %%g1, %0, %%g1\n\t"
|
|
"wrpr %%g1, 0x0, %%pstate"
|
|
: /* No outputs */
|
|
: "i" (PSTATE_IE)
|
|
: "g1");
|
|
|
|
irq_desc[0].action = &timer_irq_action;
|
|
}
|