611ae8e3f5
Not every tlb_flush execution moment is really need to evacuate all TLB entries, like in munmap, just few 'invlpg' is better for whole process performance, since it leaves most of TLB entries for later accessing. This patch also rewrite flush_tlb_range for 2 purposes: 1, split it out to get flush_blt_mm_range function. 2, clean up to reduce line breaking, thanks for Borislav's input. My micro benchmark 'mummap' http://lkml.org/lkml/2012/5/17/59 show that the random memory access on other CPU has 0~50% speed up on a 2P * 4cores * HT NHM EP while do 'munmap'. Thanks Yongjie's testing on this patch: ------------- I used Linux 3.4-RC6 w/ and w/o his patches as Xen dom0 and guest kernel. After running two benchmarks in Xen HVM guest, I found his patches brought about 1%~3% performance gain in 'kernel build' and 'netperf' testing, though the performance gain was not very stable in 'kernel build' testing. Some detailed testing results are below. Testing Environment: Hardware: Romley-EP platform Xen version: latest upstream Linux kernel: 3.4-RC6 Guest vCPU number: 8 NIC: Intel 82599 (10GB bandwidth) In 'kernel build' testing in guest: Command line | performance gain make -j 4 | 3.81% make -j 8 | 0.37% make -j 16 | -0.52% In 'netperf' testing, we tested TCP_STREAM with default socket size 16384 byte as large packet and 64 byte as small packet. I used several clients to add networking pressure, then 'netperf' server automatically generated several threads to response them. I also used large-size packet and small-size packet in the testing. Packet size | Thread number | performance gain 16384 bytes | 4 | 0.02% 16384 bytes | 8 | 2.21% 16384 bytes | 16 | 2.04% 64 bytes | 4 | 1.07% 64 bytes | 8 | 3.31% 64 bytes | 16 | 0.71% Signed-off-by: Alex Shi <alex.shi@intel.com> Link: http://lkml.kernel.org/r/1340845344-27557-8-git-send-email-alex.shi@intel.com Tested-by: Ren, Yongjie <yongjie.ren@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
178 lines
4.1 KiB
C
178 lines
4.1 KiB
C
#ifndef _ASM_X86_TLBFLUSH_H
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#define _ASM_X86_TLBFLUSH_H
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/special_insns.h>
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define __flush_tlb() __native_flush_tlb()
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#define __flush_tlb_global() __native_flush_tlb_global()
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#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
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#endif
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static inline void __native_flush_tlb(void)
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{
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native_write_cr3(native_read_cr3());
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}
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static inline void __native_flush_tlb_global(void)
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{
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unsigned long flags;
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unsigned long cr4;
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/*
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* Read-modify-write to CR4 - protect it from preemption and
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* from interrupts. (Use the raw variant because this code can
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* be called from deep inside debugging code.)
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*/
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raw_local_irq_save(flags);
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cr4 = native_read_cr4();
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/* clear PGE */
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native_write_cr4(cr4 & ~X86_CR4_PGE);
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/* write old PGE again and flush TLBs */
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native_write_cr4(cr4);
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raw_local_irq_restore(flags);
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}
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static inline void __native_flush_tlb_single(unsigned long addr)
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{
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asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
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}
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static inline void __flush_tlb_all(void)
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{
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if (cpu_has_pge)
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__flush_tlb_global();
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else
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__flush_tlb();
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}
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static inline void __flush_tlb_one(unsigned long addr)
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{
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if (cpu_has_invlpg)
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__flush_tlb_single(addr);
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else
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__flush_tlb();
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}
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#define TLB_FLUSH_ALL -1UL
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/*
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* TLB flushing:
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*
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* - flush_tlb() flushes the current mm struct TLBs
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* - flush_tlb_all() flushes all processes TLBs
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_others(cpumask, mm, start, end) flushes TLBs on other cpus
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*
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* ..but the i386 has somewhat limited tlb flushing capabilities,
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* and page-granular flushes are available only on i486 and up.
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*/
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#ifndef CONFIG_SMP
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#define flush_tlb() __flush_tlb()
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#define flush_tlb_all() __flush_tlb_all()
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#define local_flush_tlb() __flush_tlb()
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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if (mm == current->active_mm)
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__flush_tlb();
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb_one(addr);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb();
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}
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static inline void flush_tlb_mm_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end, unsigned long vmflag)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb();
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}
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static inline void native_flush_tlb_others(const struct cpumask *cpumask,
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struct mm_struct *mm,
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unsigned long start,
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unsigned long end)
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{
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}
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static inline void reset_lazy_tlbstate(void)
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{
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}
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#else /* SMP */
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#include <asm/smp.h>
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#define local_flush_tlb() __flush_tlb()
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#define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
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#define flush_tlb_range(vma, start, end) \
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flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
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extern void flush_tlb_all(void);
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extern void flush_tlb_current_task(void);
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extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
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extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
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unsigned long end, unsigned long vmflag);
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#define flush_tlb() flush_tlb_current_task()
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void native_flush_tlb_others(const struct cpumask *cpumask,
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struct mm_struct *mm,
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unsigned long start, unsigned long end);
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#define TLBSTATE_OK 1
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#define TLBSTATE_LAZY 2
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struct tlb_state {
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struct mm_struct *active_mm;
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int state;
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};
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DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
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static inline void reset_lazy_tlbstate(void)
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{
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this_cpu_write(cpu_tlbstate.state, 0);
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this_cpu_write(cpu_tlbstate.active_mm, &init_mm);
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}
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#endif /* SMP */
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#ifndef CONFIG_PARAVIRT
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#define flush_tlb_others(mask, mm, start, end) \
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native_flush_tlb_others(mask, mm, start, end)
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#endif
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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flush_tlb_all();
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}
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#endif /* _ASM_X86_TLBFLUSH_H */
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