2227b7c746
Coresight includes debug module and usually the module connects with CPU debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has description for related info in "Part H: External Debug". Chapter H7 "The Sample-based Profiling Extension" introduces several sampling registers, e.g. we can check program counter value with combined CPU exception level, secure state, etc. So this is helpful for analysis CPU lockup scenarios, e.g. if one CPU has run into infinite loop with IRQ disabled. In this case the CPU cannot switch context and handle any interrupt (including IPIs), as the result it cannot handle SMP call for stack dump. This patch is to enable coresight debug module, so firstly this driver is to bind apb clock for debug module and this is to ensure the debug module can be accessed from program or external debugger. And the driver uses sample-based registers for debug purpose, e.g. when system triggers panic, the driver will dump program counter and combined context registers (EDCIDSR, EDVIDSR); by parsing context registers so can quickly get to know CPU secure state, exception level, etc. Some of the debug module registers are located in CPU power domain, so this requires the CPU power domain stays on when access related debug registers, but the power management for CPU power domain is quite dependent on SoC integration for power management. For the platforms which with sane power controller implementations, this driver follows the method to set EDPRCR to try to pull the CPU out of low power state and then set 'no power down request' bit so the CPU has no chance to lose power. If the SoC has not followed up this design well for power management controller, the user should use the command line parameter or sysfs to constrain all or partial idle states to ensure the CPU power domain is enabled and access coresight CPU debug component safely. Signed-off-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
107 lines
4.1 KiB
Plaintext
107 lines
4.1 KiB
Plaintext
#
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# Coresight configuration
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#
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menuconfig CORESIGHT
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bool "CoreSight Tracing Support"
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select ARM_AMBA
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select PERF_EVENTS
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help
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This framework provides a kernel interface for the CoreSight debug
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and trace drivers to register themselves with. It's intended to build
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a topological view of the CoreSight components based on a DT
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specification and configure the right series of components when a
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trace source gets enabled.
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if CORESIGHT
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config CORESIGHT_LINKS_AND_SINKS
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bool "CoreSight Link and Sink drivers"
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help
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This enables support for CoreSight link and sink drivers that are
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responsible for transporting and collecting the trace data
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respectively. Link and sinks are dynamically aggregated with a trace
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entity at run time to form a complete trace path.
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config CORESIGHT_LINK_AND_SINK_TMC
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bool "Coresight generic TMC driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Trace Memory Controller driver.
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Depending on its configuration the device can act as a link (embedded
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trace router - ETR) or sink (embedded trace FIFO). The driver
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complies with the generic implementation of the component without
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special enhancement or added features.
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config CORESIGHT_SINK_TPIU
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bool "Coresight generic TPIU driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Trace Port Interface Unit driver,
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responsible for bridging the gap between the on-chip coresight
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components and a trace for bridging the gap between the on-chip
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coresight components and a trace port collection engine, typically
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connected to an external host for use case capturing more traces than
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the on-board coresight memory can handle.
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config CORESIGHT_SINK_ETBV10
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bool "Coresight ETBv1.0 driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Embedded Trace Buffer version 1.0 driver
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that complies with the generic implementation of the component without
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special enhancement or added features.
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config CORESIGHT_SOURCE_ETM3X
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bool "CoreSight Embedded Trace Macrocell 3.x driver"
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depends on !ARM64
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select CORESIGHT_LINKS_AND_SINKS
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help
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This driver provides support for processor ETM3.x and PTM1.x modules,
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which allows tracing the instructions that a processor is executing
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This is primarily useful for instruction level tracing. Depending
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the ETM version data tracing may also be available.
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config CORESIGHT_SOURCE_ETM4X
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bool "CoreSight Embedded Trace Macrocell 4.x driver"
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depends on ARM64
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select CORESIGHT_LINKS_AND_SINKS
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help
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This driver provides support for the ETM4.x tracer module, tracing the
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instructions that a processor is executing. This is primarily useful
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for instruction level tracing. Depending on the implemented version
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data tracing may also be available.
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config CORESIGHT_QCOM_REPLICATOR
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bool "Qualcomm CoreSight Replicator driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for Qualcomm CoreSight link driver. The
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programmable ATB replicator sends the ATB trace stream from the
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ETB/ETF to the TPIUi and ETR.
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config CORESIGHT_STM
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bool "CoreSight System Trace Macrocell driver"
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depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64
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select CORESIGHT_LINKS_AND_SINKS
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select STM
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help
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This driver provides support for hardware assisted software
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instrumentation based tracing. This is primarily used for
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logging useful software events or data coming from various entities
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in the system, possibly running different OSs
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config CORESIGHT_CPU_DEBUG
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tristate "CoreSight CPU Debug driver"
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depends on ARM || ARM64
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depends on DEBUG_FS
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help
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This driver provides support for coresight debugging module. This
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is primarily used to dump sample-based profiling registers when
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system triggers panic, the driver will parse context registers so
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can quickly get to know program counter (PC), secure state,
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exception level, etc. Before use debugging functionality, platform
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needs to ensure the clock domain and power domain are enabled
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properly, please refer Documentation/trace/coresight-cpu-debug.txt
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for detailed description and the example for usage.
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endif
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