52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/*
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* Copyright IBM Corp. 1999, 2009
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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/* Fast-BCR without checkpoint synchronization */
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#define mb() do { asm volatile("bcr 14,0" : : : "memory"); } while (0)
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#else
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#define mb() do { asm volatile("bcr 15,0" : : : "memory"); } while (0)
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#endif
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#define rmb() mb()
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#define wmb() mb()
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#define read_barrier_depends() do { } while(0)
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#define smp_mb__before_atomic() smp_mb()
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#define smp_mb__after_atomic() smp_mb()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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ACCESS_ONCE(*p) = (v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = ACCESS_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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#endif /* __ASM_BARRIER_H */
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