![Adrian Hunter](/assets/img/avatar_default.png)
Add support for Intel's AVX-512 instructions to the instruction decoder. AVX-512 instructions are documented in Intel Architecture Instruction Set Extensions Programming Reference (February 2016). AVX-512 instructions are identified by a EVEX prefix which, for the purpose of instruction decoding, can be treated as though it were a 4-byte VEX prefix. Existing instructions which can now accept an EVEX prefix need not be further annotated in the op code map (x86-opcode-map.txt). In the case of new instructions, the op code map is updated accordingly. Also add associated Mask Instructions that are used to manipulate mask registers used in AVX-512 instructions. The 'perf tools' instruction decoder is updated in a subsequent patch. And a representative set of instructions is added to the perf tools new instructions test in a subsequent patch. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ingo Molnar <mingo@kernel.org> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dan Williams <dan.j.williams@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: X86 ML <x86@kernel.org> Link: http://lkml.kernel.org/r/1469003437-32706-3-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
235 lines
6.3 KiB
C
235 lines
6.3 KiB
C
#ifndef _ASM_X86_INAT_H
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#define _ASM_X86_INAT_H
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/*
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* x86 instruction attributes
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*
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* Written by Masami Hiramatsu <mhiramat@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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*/
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#include <asm/inat_types.h>
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/*
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* Internal bits. Don't use bitmasks directly, because these bits are
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* unstable. You should use checking functions.
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*/
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#define INAT_OPCODE_TABLE_SIZE 256
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#define INAT_GROUP_TABLE_SIZE 8
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/* Legacy last prefixes */
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#define INAT_PFX_OPNDSZ 1 /* 0x66 */ /* LPFX1 */
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#define INAT_PFX_REPE 2 /* 0xF3 */ /* LPFX2 */
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#define INAT_PFX_REPNE 3 /* 0xF2 */ /* LPFX3 */
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/* Other Legacy prefixes */
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#define INAT_PFX_LOCK 4 /* 0xF0 */
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#define INAT_PFX_CS 5 /* 0x2E */
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#define INAT_PFX_DS 6 /* 0x3E */
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#define INAT_PFX_ES 7 /* 0x26 */
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#define INAT_PFX_FS 8 /* 0x64 */
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#define INAT_PFX_GS 9 /* 0x65 */
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#define INAT_PFX_SS 10 /* 0x36 */
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#define INAT_PFX_ADDRSZ 11 /* 0x67 */
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/* x86-64 REX prefix */
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#define INAT_PFX_REX 12 /* 0x4X */
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/* AVX VEX prefixes */
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#define INAT_PFX_VEX2 13 /* 2-bytes VEX prefix */
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#define INAT_PFX_VEX3 14 /* 3-bytes VEX prefix */
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#define INAT_PFX_EVEX 15 /* EVEX prefix */
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#define INAT_LSTPFX_MAX 3
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#define INAT_LGCPFX_MAX 11
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/* Immediate size */
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#define INAT_IMM_BYTE 1
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#define INAT_IMM_WORD 2
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#define INAT_IMM_DWORD 3
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#define INAT_IMM_QWORD 4
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#define INAT_IMM_PTR 5
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#define INAT_IMM_VWORD32 6
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#define INAT_IMM_VWORD 7
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/* Legacy prefix */
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#define INAT_PFX_OFFS 0
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#define INAT_PFX_BITS 4
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#define INAT_PFX_MAX ((1 << INAT_PFX_BITS) - 1)
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#define INAT_PFX_MASK (INAT_PFX_MAX << INAT_PFX_OFFS)
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/* Escape opcodes */
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#define INAT_ESC_OFFS (INAT_PFX_OFFS + INAT_PFX_BITS)
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#define INAT_ESC_BITS 2
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#define INAT_ESC_MAX ((1 << INAT_ESC_BITS) - 1)
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#define INAT_ESC_MASK (INAT_ESC_MAX << INAT_ESC_OFFS)
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/* Group opcodes (1-16) */
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#define INAT_GRP_OFFS (INAT_ESC_OFFS + INAT_ESC_BITS)
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#define INAT_GRP_BITS 5
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#define INAT_GRP_MAX ((1 << INAT_GRP_BITS) - 1)
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#define INAT_GRP_MASK (INAT_GRP_MAX << INAT_GRP_OFFS)
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/* Immediates */
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#define INAT_IMM_OFFS (INAT_GRP_OFFS + INAT_GRP_BITS)
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#define INAT_IMM_BITS 3
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#define INAT_IMM_MASK (((1 << INAT_IMM_BITS) - 1) << INAT_IMM_OFFS)
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/* Flags */
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#define INAT_FLAG_OFFS (INAT_IMM_OFFS + INAT_IMM_BITS)
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#define INAT_MODRM (1 << (INAT_FLAG_OFFS))
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#define INAT_FORCE64 (1 << (INAT_FLAG_OFFS + 1))
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#define INAT_SCNDIMM (1 << (INAT_FLAG_OFFS + 2))
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#define INAT_MOFFSET (1 << (INAT_FLAG_OFFS + 3))
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#define INAT_VARIANT (1 << (INAT_FLAG_OFFS + 4))
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#define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5))
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#define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6))
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#define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7))
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/* Attribute making macros for attribute tables */
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#define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS)
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#define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS)
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#define INAT_MAKE_GROUP(grp) ((grp << INAT_GRP_OFFS) | INAT_MODRM)
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#define INAT_MAKE_IMM(imm) (imm << INAT_IMM_OFFS)
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/* Attribute search APIs */
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extern insn_attr_t inat_get_opcode_attribute(insn_byte_t opcode);
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extern int inat_get_last_prefix_id(insn_byte_t last_pfx);
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extern insn_attr_t inat_get_escape_attribute(insn_byte_t opcode,
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int lpfx_id,
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insn_attr_t esc_attr);
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extern insn_attr_t inat_get_group_attribute(insn_byte_t modrm,
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int lpfx_id,
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insn_attr_t esc_attr);
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extern insn_attr_t inat_get_avx_attribute(insn_byte_t opcode,
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insn_byte_t vex_m,
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insn_byte_t vex_pp);
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/* Attribute checking functions */
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static inline int inat_is_legacy_prefix(insn_attr_t attr)
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{
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attr &= INAT_PFX_MASK;
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return attr && attr <= INAT_LGCPFX_MAX;
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}
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static inline int inat_is_address_size_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_ADDRSZ;
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}
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static inline int inat_is_operand_size_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_OPNDSZ;
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}
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static inline int inat_is_rex_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_REX;
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}
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static inline int inat_last_prefix_id(insn_attr_t attr)
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{
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if ((attr & INAT_PFX_MASK) > INAT_LSTPFX_MAX)
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return 0;
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else
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return attr & INAT_PFX_MASK;
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}
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static inline int inat_is_vex_prefix(insn_attr_t attr)
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{
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attr &= INAT_PFX_MASK;
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return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3 ||
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attr == INAT_PFX_EVEX;
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}
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static inline int inat_is_evex_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_EVEX;
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}
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static inline int inat_is_vex3_prefix(insn_attr_t attr)
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{
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return (attr & INAT_PFX_MASK) == INAT_PFX_VEX3;
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}
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static inline int inat_is_escape(insn_attr_t attr)
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{
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return attr & INAT_ESC_MASK;
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}
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static inline int inat_escape_id(insn_attr_t attr)
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{
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return (attr & INAT_ESC_MASK) >> INAT_ESC_OFFS;
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}
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static inline int inat_is_group(insn_attr_t attr)
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{
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return attr & INAT_GRP_MASK;
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}
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static inline int inat_group_id(insn_attr_t attr)
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{
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return (attr & INAT_GRP_MASK) >> INAT_GRP_OFFS;
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}
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static inline int inat_group_common_attribute(insn_attr_t attr)
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{
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return attr & ~INAT_GRP_MASK;
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}
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static inline int inat_has_immediate(insn_attr_t attr)
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{
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return attr & INAT_IMM_MASK;
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}
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static inline int inat_immediate_size(insn_attr_t attr)
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{
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return (attr & INAT_IMM_MASK) >> INAT_IMM_OFFS;
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}
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static inline int inat_has_modrm(insn_attr_t attr)
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{
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return attr & INAT_MODRM;
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}
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static inline int inat_is_force64(insn_attr_t attr)
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{
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return attr & INAT_FORCE64;
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}
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static inline int inat_has_second_immediate(insn_attr_t attr)
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{
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return attr & INAT_SCNDIMM;
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}
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static inline int inat_has_moffset(insn_attr_t attr)
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{
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return attr & INAT_MOFFSET;
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}
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static inline int inat_has_variant(insn_attr_t attr)
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{
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return attr & INAT_VARIANT;
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}
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static inline int inat_accept_vex(insn_attr_t attr)
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{
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return attr & INAT_VEXOK;
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}
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static inline int inat_must_vex(insn_attr_t attr)
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{
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return attr & (INAT_VEXONLY | INAT_EVEXONLY);
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}
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static inline int inat_must_evex(insn_attr_t attr)
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{
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return attr & INAT_EVEXONLY;
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}
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#endif
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