![Stephen Boyd](/assets/img/avatar_default.png)
The APQ8064 multimedia clock controller is fairly similar to the 8960 multimedia clock controller, except that gfx2d0/1 has been removed and the gfx3d frequency is slightly faster when using the newly introduced PLL15. We also add vcap clocks and a couple new TV clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
102 lines
3 KiB
C
102 lines
3 KiB
C
/*
|
|
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
|
|
*
|
|
* This software is licensed under the terms of the GNU General Public
|
|
* License version 2, as published by the Free Software Foundation, and
|
|
* may be copied, distributed, and modified under those terms.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H
|
|
#define _DT_BINDINGS_RESET_MSM_MMCC_8960_H
|
|
|
|
#define VPE_AXI_RESET 0
|
|
#define IJPEG_AXI_RESET 1
|
|
#define MPD_AXI_RESET 2
|
|
#define VFE_AXI_RESET 3
|
|
#define SP_AXI_RESET 4
|
|
#define VCODEC_AXI_RESET 5
|
|
#define ROT_AXI_RESET 6
|
|
#define VCODEC_AXI_A_RESET 7
|
|
#define VCODEC_AXI_B_RESET 8
|
|
#define FAB_S3_AXI_RESET 9
|
|
#define FAB_S2_AXI_RESET 10
|
|
#define FAB_S1_AXI_RESET 11
|
|
#define FAB_S0_AXI_RESET 12
|
|
#define SMMU_GFX3D_ABH_RESET 13
|
|
#define SMMU_VPE_AHB_RESET 14
|
|
#define SMMU_VFE_AHB_RESET 15
|
|
#define SMMU_ROT_AHB_RESET 16
|
|
#define SMMU_VCODEC_B_AHB_RESET 17
|
|
#define SMMU_VCODEC_A_AHB_RESET 18
|
|
#define SMMU_MDP1_AHB_RESET 19
|
|
#define SMMU_MDP0_AHB_RESET 20
|
|
#define SMMU_JPEGD_AHB_RESET 21
|
|
#define SMMU_IJPEG_AHB_RESET 22
|
|
#define SMMU_GFX2D0_AHB_RESET 23
|
|
#define SMMU_GFX2D1_AHB_RESET 24
|
|
#define APU_AHB_RESET 25
|
|
#define CSI_AHB_RESET 26
|
|
#define TV_ENC_AHB_RESET 27
|
|
#define VPE_AHB_RESET 28
|
|
#define FABRIC_AHB_RESET 29
|
|
#define GFX2D0_AHB_RESET 30
|
|
#define GFX2D1_AHB_RESET 31
|
|
#define GFX3D_AHB_RESET 32
|
|
#define HDMI_AHB_RESET 33
|
|
#define MSSS_IMEM_AHB_RESET 34
|
|
#define IJPEG_AHB_RESET 35
|
|
#define DSI_M_AHB_RESET 36
|
|
#define DSI_S_AHB_RESET 37
|
|
#define JPEGD_AHB_RESET 38
|
|
#define MDP_AHB_RESET 39
|
|
#define ROT_AHB_RESET 40
|
|
#define VCODEC_AHB_RESET 41
|
|
#define VFE_AHB_RESET 42
|
|
#define DSI2_M_AHB_RESET 43
|
|
#define DSI2_S_AHB_RESET 44
|
|
#define CSIPHY2_RESET 45
|
|
#define CSI_PIX1_RESET 46
|
|
#define CSIPHY0_RESET 47
|
|
#define CSIPHY1_RESET 48
|
|
#define DSI2_RESET 49
|
|
#define VFE_CSI_RESET 50
|
|
#define MDP_RESET 51
|
|
#define AMP_RESET 52
|
|
#define JPEGD_RESET 53
|
|
#define CSI1_RESET 54
|
|
#define VPE_RESET 55
|
|
#define MMSS_FABRIC_RESET 56
|
|
#define VFE_RESET 57
|
|
#define GFX2D0_RESET 58
|
|
#define GFX2D1_RESET 59
|
|
#define GFX3D_RESET 60
|
|
#define HDMI_RESET 61
|
|
#define MMSS_IMEM_RESET 62
|
|
#define IJPEG_RESET 63
|
|
#define CSI0_RESET 64
|
|
#define DSI_RESET 65
|
|
#define VCODEC_RESET 66
|
|
#define MDP_TV_RESET 67
|
|
#define MDP_VSYNC_RESET 68
|
|
#define ROT_RESET 69
|
|
#define TV_HDMI_RESET 70
|
|
#define TV_ENC_RESET 71
|
|
#define CSI2_RESET 72
|
|
#define CSI_RDI1_RESET 73
|
|
#define CSI_RDI2_RESET 74
|
|
#define GFX3D_AXI_RESET 75
|
|
#define VCAP_AXI_RESET 76
|
|
#define SMMU_VCAP_AHB_RESET 77
|
|
#define VCAP_AHB_RESET 78
|
|
#define CSI_RDI_RESET 79
|
|
#define CSI_PIX_RESET 80
|
|
#define VCAP_NPL_RESET 81
|
|
#define VCAP_RESET 82
|
|
|
|
#endif
|