96f60e37dc
This patch adds support for the pair of LCD controllers on the Marvell Armada 510 SoCs. This driver supports: - multiple contiguous scanout buffers for video and graphics - shm backed cacheable buffer objects for X pixmaps for Vivante GPU acceleration - dual lcd0 and lcd1 crt operation - video overlay on each LCD crt via DRM planes - page flipping of the main scanout buffers - DRM prime for buffer export/import This driver is trivial to extend to other Armada SoCs. Included in this commit is the core driver with no output support; output support is platform and encoder driver dependent. Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/*
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* Copyright (C) 2012 Russell King
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* With inspiration from the i915 driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DRM_ARMADA_IOCTL_H
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#define DRM_ARMADA_IOCTL_H
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#define DRM_ARMADA_GEM_CREATE 0x00
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#define DRM_ARMADA_GEM_MMAP 0x02
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#define DRM_ARMADA_GEM_PWRITE 0x03
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#define ARMADA_IOCTL(dir, name, str) \
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DRM_##dir(DRM_COMMAND_BASE + DRM_ARMADA_##name, struct drm_armada_##str)
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struct drm_armada_gem_create {
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uint32_t handle;
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uint32_t size;
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};
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#define DRM_IOCTL_ARMADA_GEM_CREATE \
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ARMADA_IOCTL(IOWR, GEM_CREATE, gem_create)
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struct drm_armada_gem_mmap {
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uint32_t handle;
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uint32_t pad;
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uint64_t offset;
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uint64_t size;
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uint64_t addr;
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};
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#define DRM_IOCTL_ARMADA_GEM_MMAP \
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ARMADA_IOCTL(IOWR, GEM_MMAP, gem_mmap)
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struct drm_armada_gem_pwrite {
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uint64_t ptr;
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uint32_t handle;
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uint32_t offset;
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uint32_t size;
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};
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#define DRM_IOCTL_ARMADA_GEM_PWRITE \
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ARMADA_IOCTL(IOW, GEM_PWRITE, gem_pwrite)
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#endif
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