789 lines
15 KiB
ArmAsm
789 lines
15 KiB
ArmAsm
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#define PM_INFO_VBASE_OFFSET 0x0
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#define PM_INFO_PBASE_OFFSET 0x4
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#define PM_INFO_RESUME_ADDR_OFFSET 0x8
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#define PM_INFO_PM_INFO_SIZE_OFFSET 0xc
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#define PM_INFO_PM_INFO_TTBR_OFFSET 0x10
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#define PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET 0x14
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#define PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET 0x18
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#define PM_INFO_VAL_OFFSET 0x1c
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#define PM_INFO_FLAG0_OFFSET 0x20
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#define PM_INFO_FLAG1_OFFSET 0x24
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#define PM_INFO_MX7D_DDRC_P_OFFSET 0x28
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#define PM_INFO_MX7D_DDRC_V_OFFSET 0x2c
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#define PM_INFO_MX7D_CCM_P_OFFSET 0x30
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#define PM_INFO_MX7D_CCM_V_OFFSET 0x34
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#define PM_INFO_MX7D_ANATOP_P_OFFSET 0x38
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#define PM_INFO_MX7D_ANATOP_V_OFFSET 0x3c
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#define PM_INFO_MX7D_SRC_P_OFFSET 0x40
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#define PM_INFO_MX7D_SRC_V_OFFSET 0x44
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#define PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET 0x48
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#define PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET 0x4c
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#define PM_INFO_MX7D_GPC_P_OFFSET 0x50
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#define PM_INFO_MX7D_GPC_V_OFFSET 0x54
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#define PM_INFO_MX7D_GIC_DIST_P_OFFSET 0x58
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#define PM_INFO_MX7D_GIC_DIST_V_OFFSET 0x5c
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#define MX7D_SRC_GPR1 0x74
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#define MX7D_SRC_GPR2 0x78
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#define MX7D_SRC_GPR3 0x7c
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#define MX7D_SRC_GPR4 0x80
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#define MX7D_GPC_IMR1 0x30
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#define MX7D_GPC_IMR2 0x34
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#define MX7D_GPC_IMR3 0x38
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#define MX7D_GPC_IMR4 0x3c
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#define DDRC_STAT 0x4
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#define DDRC_PWRCTL 0x30
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#define DDRC_DBG1 0x304
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#define DDRC_DBGCAM 0x308
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#define DDRC_PSTAT 0x3fc
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#define DDRC_PCTRL_0 0x490
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/*
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* imx_pen_lock
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*
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* The reference link of Peterson's algorithm:
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* http://en.wikipedia.org/wiki/Peterson's_algorithm
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*
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* val1 = r1 = !turn (inverted from Peterson's algorithm)
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* on cpu 0:
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* r2 = flag[0] (in flag0)
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* r3 = flag[1] (in flag1)
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* on cpu1:
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* r2 = flag[1] (in flag1)
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* r3 = flag[0] (in flag0)
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*
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*/
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.macro imx_pen_lock
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mov r8, r0
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mrc p15, 0, r5, c0, c0, 5
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and r5, r5, #3
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add r6, r8, #PM_INFO_VAL_OFFSET
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cmp r5, #0
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addeq r7, r8, #PM_INFO_FLAG0_OFFSET
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addeq r8, r8, #PM_INFO_FLAG1_OFFSET
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addne r7, r8, #PM_INFO_FLAG1_OFFSET
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addne r8, r8, #PM_INFO_FLAG0_OFFSET
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mov r9, #1
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str r9, [r7]
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dsb
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str r5, [r6]
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1:
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dsb
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ldr r9, [r8]
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cmp r9, #1
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ldreq r9, [r6]
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cmpeq r9, r5
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beq 1b
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.endm
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.macro imx_pen_unlock
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dsb
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mrc p15, 0, r6, c0, c0, 5
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and r6, r6, #3
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cmp r6, #0
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addeq r7, r0, #PM_INFO_FLAG0_OFFSET
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addne r7, r0, #PM_INFO_FLAG1_OFFSET
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mov r9, #0
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str r9, [r7]
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.endm
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.macro disable_l1_dcache
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push {r0 - r12, lr}
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ldr r7, =v7_flush_dcache_all
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mov lr, pc
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mov pc, r7
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pop {r0 - r12, lr}
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/* disable d-cache */
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mrc p15, 0, r7, c1, c0, 0
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bic r7, r7, #(1 << 2)
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mcr p15, 0, r7, c1, c0, 0
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dsb
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isb
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push {r0 - r12, lr}
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ldr r7, =v7_flush_dcache_all
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mov lr, pc
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mov pc, r7
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pop {r0 - r12, lr}
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#ifdef CONFIG_SMP
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clrex
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/* Turn off SMP bit. */
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mrc p15, 0, r8, c1, c0, 1
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bic r8, r8, #0x40
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mcr p15, 0, r8, c1, c0, 1
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isb
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dsb
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#endif
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.endm
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.macro tlb_set_to_ocram
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/* save ttbr */
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mrc p15, 0, r7, c2, c0, 1
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str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET]
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/*
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* To ensure no page table walks occur in DDR, we
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* have a another page table stored in IRAM that only
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* contains entries pointing to IRAM, AIPS1 and AIPS2.
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* We need to set the TTBR1 to the new IRAM TLB.
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* Do the following steps:
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* 1. Flush the Branch Target Address Cache (BTAC)
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* 2. Set TTBR1 to point to IRAM page table.
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* 3. Disable page table walks in TTBR0 (PD0 = 1)
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* 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
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* and 2-4G is translated by TTBR1.
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*/
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/* Disable Branch Prediction, Z bit in SCTLR. */
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mrc p15, 0, r6, c1, c0, 0
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bic r6, r6, #0x800
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mcr p15, 0, r6, c1, c0, 0
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/* Flush the BTAC. */
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ldr r6, =0x0
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mcr p15, 0, r6, c7, c1, 6
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ldr r6, =iram_tlb_phys_addr
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ldr r7, [r6]
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dsb
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isb
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/* Store the IRAM table in TTBR1 */
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mcr p15, 0, r7, c2, c0, 1
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/* Read TTBCR and set PD0=1, N = 1 */
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mrc p15, 0, r6, c2, c0, 2
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orr r6, r6, #0x11
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mcr p15, 0, r6, c2, c0, 2
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dsb
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isb
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/* flush the TLB */
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ldr r6, =0x0
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mcr p15, 0, r6, c8, c3, 0
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.endm
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.macro tlb_back_to_ddr
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/* Read TTBCR and set PD0=0, N = 0 */
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mrc p15, 0, r6, c2, c0, 2
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bic r6, r6, #0x11
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mcr p15, 0, r6, c2, c0, 2
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dsb
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isb
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/* flush the TLB */
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ldr r6, =0x0
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mcr p15, 0, r6, c8, c3, 0
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/* Enable Branch Prediction, Z bit in SCTLR. */
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mrc p15, 0, r6, c1, c0, 0
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orr r6, r6, #0x800
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mcr p15, 0, r6, c1, c0, 0
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/* Flush the Branch Target Address Cache (BTAC) */
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ldr r6, =0x0
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mcr p15, 0, r6, c7, c1, 6
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/* restore ttbr */
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ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET]
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mcr p15, 0, r7, c2, c0, 1
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.endm
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/* r10 must be DDRC base address */
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.macro ddrc_enter_self_refresh
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ldr r10, [r0, #PM_INFO_MX7D_DDRC_V_OFFSET]
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/* disable port */
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ldr r7, =0x0
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str r7, [r10, #DDRC_PCTRL_0]
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/* let DDR out of self-refresh */
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ldr r7, =0x0
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str r7, [r10, #DDRC_PWRCTL]
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/* wait rw port_busy clear */
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ldr r6, =(0x1 << 16)
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orr r6, r6, #0x1
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2:
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ldr r7, [r10, #DDRC_PSTAT]
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ands r7, r7, r6
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bne 2b
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ldr r7, =0x1
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str r7, [r10, #DDRC_DBG1]
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ldr r6, =0x36000000
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11:
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ldr r7, [r10, #DDRC_DBGCAM]
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and r7, r7, r6
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cmp r7, r6
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bne 11b
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/* enter self-refresh bit 5 */
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ldr r7, =(0x1 << 5)
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str r7, [r10, #DDRC_PWRCTL]
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/* wait until self-refresh mode entered */
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3:
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ldr r7, [r10, #DDRC_STAT]
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and r7, r7, #0x3
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cmp r7, #0x3
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bne 3b
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4:
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ldr r7, [r10, #DDRC_STAT]
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ands r7, r7, #0x20
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beq 4b
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/* disable dram clk */
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ldr r7, [r10, #DDRC_PWRCTL]
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orr r7, r7, #(1 << 3)
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str r7, [r10, #DDRC_PWRCTL]
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/*
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* TO1.1 adds feature of DDR pads power down,
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* although TO1.0 has no such function, but it is
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* NOT harmful to program GPR registers for TO1.0,
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* it can avoid the logic of version check in idle
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* thread.
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*/
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ldr r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET]
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ldr r7, =0xf0000
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str r7, [r10]
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/* delay 20us, measured by gpio */
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ldr r7, =20
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12:
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subs r7, r7, #0x1
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bne 12b
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.endm
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/* r10 must be DDRC base address */
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.macro ddrc_exit_self_refresh
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cmp r5, #0x1
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ldreq r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_P_OFFSET]
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ldrne r10, [r0, #PM_INFO_MX7D_IOMUXC_GPR_V_OFFSET]
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ldr r7, =0x0
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str r7, [r10]
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ldr r7, =20
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13:
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subs r7, r7, #0x1
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bne 13b
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cmp r5, #0x1
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ldreq r10, [r0, #PM_INFO_MX7D_DDRC_P_OFFSET]
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ldrne r10, [r0, #PM_INFO_MX7D_DDRC_V_OFFSET]
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ldr r7, =0x0
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str r7, [r10, #DDRC_DBG1]
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ldr r6, =0x30000000
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14:
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ldr r7, [r10, #DDRC_DBGCAM]
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and r7, r7, r6
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cmp r7, r6
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bne 14b
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/* let DDR out of self-refresh */
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ldr r7, =0x0
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str r7, [r10, #DDRC_PWRCTL]
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/* wait until self-refresh mode exited */
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5:
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ldr r7, [r10, #DDRC_STAT]
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and r7, r7, #0x3
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cmp r7, #0x3
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beq 5b
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/* enable auto self-refresh */
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ldr r7, [r10, #DDRC_PWRCTL]
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orr r7, r7, #(1 << 0)
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str r7, [r10, #DDRC_PWRCTL]
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ldr r7, =0x1
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str r7, [r10, #DDRC_PCTRL_0]
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.endm
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.macro pll_do_wait_lock
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6:
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ldr r7, [r10, r8]
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ands r7, #0x80000000
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beq 6b
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.endm
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.macro ccm_enter_idle
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ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET]
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/* ungate pfd1 332m for lower axi */
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ldr r7, =0x8000
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str r7, [r10, #0xc8]
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ldr r10, [r0, #PM_INFO_MX7D_CCM_V_OFFSET]
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/* switch ARM CLK to OSC */
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ldr r8, =0x8000
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ldr r7, [r10, r8]
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bic r7, r7, #0x7000000
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str r7, [r10, r8]
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/* lower AXI clk from 24MHz to 3MHz */
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ldr r8, =0x8800
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ldr r7, [r10, r8]
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orr r7, r7, #0x7
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str r7, [r10, r8]
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/* lower AHB clk from 24MHz to 3MHz */
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ldr r8, =0x9000
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ldr r7, [r10, r8]
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orr r7, r7, #0x7
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str r7, [r10, r8]
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/* gate dram clk */
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ldr r8, =0x9880
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ldr r7, [r10, r8]
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bic r7, r7, #0x10000000
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str r7, [r10, r8]
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ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET]
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/* gate pfd1 332m */
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ldr r7, =0x8000
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str r7, [r10, #0xc4]
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/* gate system pll pfd div 1 */
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ldr r7, =0x10
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str r7, [r10, #0xb4]
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/* power down ARM, 480 and DRAM PLL */
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ldr r7, =0x1000
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str r7, [r10, #0x64]
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str r7, [r10, #0xb4]
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ldr r7, =0x100000
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str r7, [r10, #0x74]
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.endm
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.macro ccm_exit_idle
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cmp r5, #0x1
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ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET]
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ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET]
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/* power up ARM, 480 and DRAM PLL */
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ldr r7, =0x1000
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str r7, [r10, #0x68]
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ldr r8, =0x60
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pll_do_wait_lock
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ldr r7, =0x1000
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str r7, [r10, #0xb8]
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ldr r8, =0xb0
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pll_do_wait_lock
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ldr r7, =0x100000
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str r7, [r10, #0x78]
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ldr r8, =0x70
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pll_do_wait_lock
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/* ungate pfd1 332m for lower axi */
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ldr r7, =0x8000
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str r7, [r10, #0xc8]
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/* ungate system pll pfd div 1 */
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ldr r7, =0x10
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str r7, [r10, #0xb8]
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cmp r5, #0x1
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ldreq r10, [r0, #PM_INFO_MX7D_CCM_P_OFFSET]
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ldrne r10, [r0, #PM_INFO_MX7D_CCM_V_OFFSET]
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/* switch ARM CLK to PLL */
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ldr r8, =0x8000
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ldr r7, [r10, r8]
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orr r7, r7, #0x1000000
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str r7, [r10, r8]
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/* restore AXI clk from 3MHz to 24MHz */
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ldr r8, =0x8800
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ldr r7, [r10, r8]
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bic r7, r7, #0x7
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str r7, [r10, r8]
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/* restore AHB clk from 3MHz to 24MHz */
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ldr r8, =0x9000
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ldr r7, [r10, r8]
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bic r7, r7, #0x7
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str r7, [r10, r8]
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/* ungate dram clk */
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ldr r8, =0x9880
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ldr r7, [r10, r8]
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orr r7, r7, #0x10000000
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str r7, [r10, r8]
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cmp r5, #0x1
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ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET]
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ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET]
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/* gate pfd1 332m for lower axi */
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ldr r7, =0x8000
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str r7, [r10, #0xc4]
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.endm
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.macro anatop_enter_idle
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ldr r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET]
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/* XTAL to RC-OSC switch */
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ldr r7, [r10]
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orr r7, r7, #0x1000
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str r7, [r10]
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/* power down XTAL */
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ldr r7, [r10]
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orr r7, r7, #0x1
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str r7, [r10]
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/* enable weak 1P0A */
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ldr r7, [r10, #0x200]
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orr r7, r7, #0x40000
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str r7, [r10, #0x200]
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/* disable LDO 1P0A */
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ldr r7, [r10, #0x200]
|
|
bic r7, r7, #0x1
|
|
str r7, [r10, #0x200]
|
|
|
|
/* disable LDO 1P0D */
|
|
ldr r7, [r10, #0x210]
|
|
bic r7, r7, #0x1
|
|
str r7, [r10, #0x210]
|
|
|
|
/* disable LDO 1P2 */
|
|
ldr r7, [r10, #0x220]
|
|
bic r7, r7, #0x1
|
|
str r7, [r10, #0x220]
|
|
|
|
/* switch to low power bandgap */
|
|
ldr r7, [r10, #0x270]
|
|
orr r7, r7, #0x400
|
|
str r7, [r10, #0x270]
|
|
/* power down normal bandgap */
|
|
orr r7, r7, #0x1
|
|
str r7, [r10, #0x270]
|
|
|
|
.endm
|
|
|
|
.macro anatop_exit_idle
|
|
|
|
cmp r5, #0x1
|
|
ldreq r10, [r0, #PM_INFO_MX7D_ANATOP_P_OFFSET]
|
|
ldrne r10, [r0, #PM_INFO_MX7D_ANATOP_V_OFFSET]
|
|
|
|
/* power on normal bandgap */
|
|
ldr r7, [r10, #0x270]
|
|
bic r7, r7, #0x1
|
|
str r7, [r10, #0x270]
|
|
/* switch to normal bandgap */
|
|
bic r7, r7, #0x400
|
|
str r7, [r10, #0x270]
|
|
|
|
/* enable LDO 1P2 */
|
|
ldr r7, [r10, #0x220]
|
|
orr r7, r7, #0x1
|
|
str r7, [r10, #0x220]
|
|
7:
|
|
ldr r7, [r10, #0x220]
|
|
ands r7, #0x20000
|
|
beq 7b
|
|
|
|
/* enable LDO 1P0D */
|
|
ldr r7, [r10, #0x210]
|
|
orr r7, r7, #0x1
|
|
str r7, [r10, #0x210]
|
|
8:
|
|
ldr r7, [r10, #0x210]
|
|
ands r7, #0x20000
|
|
beq 8b
|
|
|
|
/* enable LDO 1P0A */
|
|
ldr r7, [r10, #0x200]
|
|
orr r7, r7, #0x1
|
|
str r7, [r10, #0x200]
|
|
9:
|
|
ldr r7, [r10, #0x200]
|
|
ands r7, #0x20000
|
|
beq 9b
|
|
/* disable weak 1P0A */
|
|
ldr r7, [r10, #0x200]
|
|
bic r7, r7, #0x40000
|
|
str r7, [r10, #0x200]
|
|
|
|
/* power up XTAL and wait */
|
|
ldr r7, [r10]
|
|
bic r7, r7, #0x1
|
|
str r7, [r10]
|
|
10:
|
|
ldr r7, [r10]
|
|
ands r7, r7, #0x4
|
|
beq 10b
|
|
/* RC-OSC to XTAL switch */
|
|
ldr r7, [r10]
|
|
bic r7, r7, #0x1000
|
|
str r7, [r10]
|
|
|
|
.endm
|
|
|
|
.extern iram_tlb_phys_addr
|
|
|
|
.align 3
|
|
ENTRY(imx7d_low_power_idle)
|
|
push {r0 - r12}
|
|
|
|
/* get necessary info from pm_info */
|
|
ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
|
|
ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
|
|
|
|
/*
|
|
* counting the resume address in iram
|
|
* to set it in SRC register.
|
|
*/
|
|
ldr r5, =imx7d_low_power_idle
|
|
ldr r6, =wakeup
|
|
sub r6, r6, r5
|
|
add r8, r1, r2
|
|
add r3, r8, r6
|
|
|
|
/* r11 is cpu id */
|
|
mrc p15, 0, r11, c0, c0, 5
|
|
and r11, r11, #3
|
|
cmp r11, #0x0
|
|
ldreq r6, =MX7D_SRC_GPR1
|
|
ldreq r7, =MX7D_SRC_GPR2
|
|
ldrne r6, =MX7D_SRC_GPR3
|
|
ldrne r7, =MX7D_SRC_GPR4
|
|
/* store physical resume addr and pm_info address. */
|
|
ldr r10, [r0, #PM_INFO_MX7D_SRC_V_OFFSET]
|
|
str r3, [r10, r6]
|
|
str r1, [r10, r7]
|
|
|
|
disable_l1_dcache
|
|
|
|
tlb_set_to_ocram
|
|
|
|
/* check last to sleep */
|
|
ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET]
|
|
ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET]
|
|
cmp r6, r7
|
|
bne lpi_enter_done
|
|
|
|
ddrc_enter_self_refresh
|
|
ccm_enter_idle
|
|
anatop_enter_idle
|
|
|
|
ldr r10, [r0, #PM_INFO_MX7D_GIC_DIST_V_OFFSET]
|
|
ldr r7, =0x0
|
|
ldr r8, =0x1000
|
|
str r7, [r10, r8]
|
|
|
|
ldr r10, [r0, #PM_INFO_MX7D_GPC_V_OFFSET]
|
|
ldr r4, [r10, #MX7D_GPC_IMR1]
|
|
ldr r5, [r10, #MX7D_GPC_IMR2]
|
|
ldr r6, [r10, #MX7D_GPC_IMR3]
|
|
ldr r7, [r10, #MX7D_GPC_IMR4]
|
|
|
|
ldr r8, =0xffffffff
|
|
str r8, [r10, #MX7D_GPC_IMR1]
|
|
str r8, [r10, #MX7D_GPC_IMR2]
|
|
str r8, [r10, #MX7D_GPC_IMR3]
|
|
str r8, [r10, #MX7D_GPC_IMR4]
|
|
|
|
/*
|
|
* enable the RBC bypass counter here
|
|
* to hold off the interrupts. RBC counter
|
|
* = 8 (240us). With this setting, the latency
|
|
* from wakeup interrupt to ARM power up
|
|
* is ~250uS.
|
|
*/
|
|
ldr r8, [r10, #0x14]
|
|
bic r8, r8, #(0x3f << 24)
|
|
orr r8, r8, #(0x8 << 24)
|
|
str r8, [r10, #0x14]
|
|
|
|
/* enable the counter. */
|
|
ldr r8, [r10, #0x14]
|
|
orr r8, r8, #(0x1 << 30)
|
|
str r8, [r10, #0x14]
|
|
|
|
/* unmask all the GPC interrupts. */
|
|
str r4, [r10, #MX7D_GPC_IMR1]
|
|
str r5, [r10, #MX7D_GPC_IMR2]
|
|
str r6, [r10, #MX7D_GPC_IMR3]
|
|
str r7, [r10, #MX7D_GPC_IMR4]
|
|
|
|
/*
|
|
* now delay for a short while (30usec)
|
|
* ARM is at 24MHz at this point
|
|
* so a short loop should be enough.
|
|
* this delay is required to ensure that
|
|
* the RBC counter can start counting in
|
|
* case an interrupt is already pending
|
|
* or in case an interrupt arrives just
|
|
* as ARM is about to assert DSM_request.
|
|
*/
|
|
ldr r4, =5
|
|
rbc_loop:
|
|
subs r4, r4, #0x1
|
|
bne rbc_loop
|
|
|
|
lpi_enter_done:
|
|
|
|
imx_pen_unlock
|
|
|
|
wfi
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
imx_pen_lock
|
|
|
|
/* check first to wake */
|
|
ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET]
|
|
ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET]
|
|
cmp r6, r7
|
|
bne skip_lpi_flow
|
|
|
|
ldr r5, =0x0
|
|
anatop_exit_idle
|
|
ccm_exit_idle
|
|
ddrc_exit_self_refresh
|
|
|
|
ldr r10, [r0, #PM_INFO_MX7D_GIC_DIST_V_OFFSET]
|
|
ldr r7, =0x1
|
|
ldr r8, =0x1000
|
|
str r7, [r10, r8]
|
|
|
|
skip_lpi_flow:
|
|
tlb_back_to_ddr
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* Turn on SMP bit. */
|
|
mrc p15, 0, r7, c1, c0, 1
|
|
orr r7, r7, #0x40
|
|
mcr p15, 0, r7, c1, c0, 1
|
|
|
|
isb
|
|
#endif
|
|
|
|
/* enable d-cache */
|
|
mrc p15, 0, r7, c1, c0, 0
|
|
orr r7, r7, #(1 << 2)
|
|
mcr p15, 0, r7, c1, c0, 0
|
|
dsb
|
|
isb
|
|
|
|
/* Restore registers */
|
|
pop {r0 - r12}
|
|
mov pc, lr
|
|
|
|
wakeup:
|
|
|
|
/* invalidate L1 I-cache first */
|
|
mov r1, #0x0
|
|
mcr p15, 0, r1, c7, c5, 0
|
|
mcr p15, 0, r1, c7, c5, 0
|
|
mcr p15, 0, r1, c7, c5, 6
|
|
/* enable the Icache and branch prediction */
|
|
mov r1, #0x1800
|
|
mcr p15, 0, r1, c1, c0, 0
|
|
isb
|
|
|
|
imx_pen_lock
|
|
|
|
/* check first to wake */
|
|
ldr r6, [r0, #PM_INFO_PM_INFO_NUM_ONLINE_CPUS_OFFSET]
|
|
ldr r7, [r0, #PM_INFO_PM_INFO_NUM_LPI_CPUS_OFFSET]
|
|
cmp r6, r7
|
|
bne wakeup_skip_lpi_flow
|
|
|
|
ldr r5, =0x1
|
|
anatop_exit_idle
|
|
ccm_exit_idle
|
|
ddrc_exit_self_refresh
|
|
|
|
wakeup_skip_lpi_flow:
|
|
/* get physical resume address from pm_info. */
|
|
ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
|
|
|
|
/* Restore registers */
|
|
mov pc, lr
|
|
.ltorg
|
|
ENDPROC(imx7d_low_power_idle)
|