3cd2c313f1
On the CP110 components which are present on the Armada 7K/8K SoC we need to explicitly enable the clock for the registers. However it is not needed for the AP8xx component, that's why this clock is optional. With this patch both clock have now a name, but in order to be backward compatible, the name of the first clock is not used. It allows to still use this clock with a device tree using the old binding. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
29 lines
765 B
Plaintext
29 lines
765 B
Plaintext
* Marvell XOR v2 engines
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Required properties:
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- compatible: one of the following values:
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"marvell,armada-7k-xor"
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"marvell,xor-v2"
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- reg: Should contain registers location and length (two sets)
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the first set is the DMA registers
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the second set is the global registers
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- msi-parent: Phandle to the MSI-capable interrupt controller used for
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interrupts.
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Optional properties:
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- clocks: Optional reference to the clocks used by the XOR engine.
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- clock-names: mandatory if there is a second clock, in this case the
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name must be "core" for the first clock and "reg" for the second
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one
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Example:
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xor0@400000 {
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compatible = "marvell,xor-v2";
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reg = <0x400000 0x1000>,
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<0x410000 0x1000>;
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msi-parent = <&gic_v2m0>;
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dma-coherent;
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};
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