0a45dcab22
add support for new CSR atlas7 SoC. atlas7 exists V1 and V2 IP. atlas7 DMAv1 is basically moved from marco, which has never been delivered to customers and renamed in this patch. atlas7 DMAv2 supports chain DMA by a chain table, this patch also adds chain DMA support for atlas7. atlas7 DMAv1 and DMAv2 co-exist in the same chip. there are some HW configuration differences(register offset etc.) with old prima2 chips, so we use compatible string to differentiate old prima2 and new atlas7, then results in different set in HW for them. Signed-off-by: Hao Liu <Hao.Liu@csr.com> Signed-off-by: Yanchang Li <Yanchang.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
45 lines
1.1 KiB
Plaintext
45 lines
1.1 KiB
Plaintext
* CSR SiRFSoC DMA controller
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See dma.txt first
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Required properties:
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- compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or
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"sirf,atlas7-dmac-v2"
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- reg: Should contain DMA registers location and length.
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- interrupts: Should contain one interrupt shared by all channel
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- #dma-cells: must be <1>. used to represent the number of integer
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cells in the dmas property of client device.
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- clocks: clock required
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Example:
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Controller:
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dmac0: dma-controller@b00b0000 {
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compatible = "sirf,prima2-dmac";
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reg = <0xb00b0000 0x10000>;
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interrupts = <12>;
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clocks = <&clks 24>;
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#dma-cells = <1>;
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};
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Client:
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Fill the specific dma request line in dmas. In the below example, spi0 read
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channel request line is 9 of the 2nd dma controller, while write channel uses
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4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st
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dma controller, while write channel uses 13 of the 1st dma controller:
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spi0: spi@b00d0000 {
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compatible = "sirf,prima2-spi";
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dmas = <&dmac1 9>,
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<&dmac1 4>;
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dma-names = "rx", "tx";
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};
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spi1: spi@b0170000 {
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compatible = "sirf,prima2-spi";
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dmas = <&dmac0 12>,
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<&dmac0 13>;
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dma-names = "rx", "tx";
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};
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