7c7055c7c5
This bitfield intends to address features to be activated within the driver. Initially the mask was only meant for FIFO Threshold management. Backward compatibility is preserved but the meaning of this field has been extended to features instead of only threshold. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
84 lines
2.4 KiB
Plaintext
84 lines
2.4 KiB
Plaintext
* STMicroelectronics STM32 DMA controller
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The STM32 DMA is a general-purpose direct memory access controller capable of
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supporting 8 independent DMA channels. Each channel can have up to 8 requests.
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Required properties:
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- compatible: Should be "st,stm32-dma"
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- reg: Should contain DMA registers location and length. This should include
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all of the per-channel registers.
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- interrupts: Should contain all of the per-channel DMA interrupts in
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ascending order with respect to the DMA channel index.
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- clocks: Should contain the input clock of the DMA instance.
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- #dma-cells : Must be <4>. See DMA client paragraph for more details.
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Optional properties:
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- dma-requests : Number of DMA requests supported.
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- resets: Reference to a reset controller asserting the DMA controller
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- st,mem2mem: boolean; if defined, it indicates that the controller supports
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memory-to-memory transfer
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Example:
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dma2: dma-controller@40026400 {
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compatible = "st,stm32-dma";
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reg = <0x40026400 0x400>;
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interrupts = <56>,
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<57>,
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<58>,
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<59>,
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<60>,
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<68>,
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<69>,
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<70>;
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clocks = <&clk_hclk>;
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#dma-cells = <4>;
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st,mem2mem;
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resets = <&rcc 150>;
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dma-requests = <8>;
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};
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* DMA client
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DMA clients connected to the STM32 DMA controller must use the format
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described in the dma.txt file, using a four-cell specifier for each
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channel: a phandle to the DMA controller plus the following four integer cells:
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1. The channel id
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2. The request line number
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3. A 32bit mask specifying the DMA channel configuration which are device
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dependent:
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-bit 9: Peripheral Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 10: Memory Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 15: Peripheral Increment Offset Size
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0x0: offset size is linked to the peripheral bus width
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0x1: offset size is fixed to 4 (32-bit alignment)
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-bit 16-17: Priority level
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0x0: low
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0x1: medium
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0x2: high
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0x3: very high
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4. A 32bit bitfield value specifying DMA features which are device dependent:
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-bit 0-1: DMA FIFO threshold selection
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0x0: 1/4 full FIFO
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0x1: 1/2 full FIFO
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0x2: 3/4 full FIFO
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0x3: full FIFO
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Example:
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usart1: serial@40011000 {
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compatible = "st,stm32-uart";
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reg = <0x40011000 0x400>;
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interrupts = <37>;
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clocks = <&clk_pclk2>;
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dmas = <&dma2 2 4 0x10400 0x3>,
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<&dma2 7 5 0x10200 0x3>;
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dma-names = "rx", "tx";
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};
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