774dfc9bb7
DT passes the exact GART register ranges without any overlapping with MC register ranges. GART register offset needs to be adjusted by one passed by DT correctly. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
15 lines
391 B
Plaintext
15 lines
391 B
Plaintext
NVIDIA Tegra 20 GART
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Required properties:
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- compatible: "nvidia,tegra20-gart"
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- reg: Two pairs of cells specifying the physical address and size of
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the memory controller registers and the GART aperture respectively.
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Example:
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gart {
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compatible = "nvidia,tegra20-gart";
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reg = <0x7000f024 0x00000018 /* controller registers */
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0x58000000 0x02000000>; /* GART aperture */
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};
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