a8b70ccf10
To improve eye diagram for PHYs on different boards of same SOC, some parameters may need to be changed. Provide device tree properties to override these from board specific device tree files. While at it, replace "qcom,qusb2-v2-phy" with compatible string for USB2 PHY on sdm845 which was earlier added for sdm845 only. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
68 lines
2.6 KiB
Plaintext
68 lines
2.6 KiB
Plaintext
Qualcomm QUSB2 phy controller
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QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
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Required properties:
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- compatible: compatible list, contains
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"qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
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"qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
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- reg: offset and length of the PHY register set.
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- #phy-cells: must be 0.
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: must be "cfg_ahb" for phy config clock,
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"ref" for 19.2 MHz ref clk,
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"iface" for phy interface clock (Optional).
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- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
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- vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
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- resets: Phandle to reset to phy block.
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Optional properties:
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- nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
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tuning parameter value for qusb2 phy.
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- qcom,tcsr-syscon: Phandle to TCSR syscon register region.
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- qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be
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added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
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tuning parameter that may vary for different boards of same SOC.
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This property is applicable to only QUSB2 v2 PHY (sdm845).
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- qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX
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output current.
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Possible range is - 15mA to 24mA (stepsize of 600 uA).
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See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
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This property is applicable to only QUSB2 v2 PHY (sdm845).
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Default value is 22.2mA for sdm845.
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- qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level.
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Possible range is 0 to 15% (stepsize of 5%).
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See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
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This property is applicable to only QUSB2 v2 PHY (sdm845).
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Default value is 10% for sdm845.
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- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX
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pre-emphasis (specified using qcom,preemphasis-level) must be in
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effect. Duration could be half-bit of full-bit.
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See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
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This property is applicable to only QUSB2 v2 PHY (sdm845).
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Default value is full-bit width for sdm845.
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Example:
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hsusb_phy: phy@7411000 {
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compatible = "qcom,msm8996-qusb2-phy";
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reg = <0x7411000 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_RX1_USB2_CLKREF_CLK>,
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clock-names = "cfg_ahb", "ref";
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vdda-pll-supply = <&pm8994_l12>;
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vdda-phy-dpdm-supply = <&pm8994_l24>;
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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nvmem-cells = <&qusb2p_hstx_trim>;
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};
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