e40ff1d660
When L1 IOAPIC redirection-table is written, a request of KVM_REQ_SCAN_IOAPIC is set on all vCPUs. This is done such that all vCPUs will now recalc their IOAPIC handled vectors and load it to their EOI-exitmap. However, it could be that one of the vCPUs is currently running L2. In this case, load_eoi_exitmap() will be called which would write to vmcs02->eoi_exit_bitmap, which is wrong because vmcs02->eoi_exit_bitmap should always be equal to vmcs12->eoi_exit_bitmap. Furthermore, at this point KVM_REQ_SCAN_IOAPIC was already consumed and therefore we will never update vmcs01->eoi_exit_bitmap. This could lead to remote_irr of some IOAPIC level-triggered entry to remain set forever. Fix this issue by delaying the load of EOI-exitmap to when vCPU is running L1. One may wonder why not just delay entire KVM_REQ_SCAN_IOAPIC processing to when vCPU is running L1. This is done in order to handle correctly the case where LAPIC & IO-APIC of L1 is pass-throughed into L2. In this case, vmcs12->virtual_interrupt_delivery should be 0. In current nVMX implementation, that results in vmcs02->virtual_interrupt_delivery to also be 0. Thus, vmcs02->eoi_exit_bitmap is not used. Therefore, every L2 EOI cause a #VMExit into L0 (either on MSR_WRITE to x2APIC MSR or APIC_ACCESS/APIC_WRITE/EPT_MISCONFIG to APIC MMIO page). In order for such L2 EOI to be broadcasted, if needed, from LAPIC to IO-APIC, vcpu->arch.ioapic_handled_vectors must be updated while L2 is running. Therefore, patch makes sure to delay only the loading of EOI-exitmap but not the update of vcpu->arch.ioapic_handled_vectors. Reviewed-by: Arbel Moshe <arbel.moshe@oracle.com> Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ASM_KVM_CACHE_REGS_H
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#define ASM_KVM_CACHE_REGS_H
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#define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS
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#define KVM_POSSIBLE_CR4_GUEST_BITS \
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(X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
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| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_PGE)
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static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu,
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enum kvm_reg reg)
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{
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if (!test_bit(reg, (unsigned long *)&vcpu->arch.regs_avail))
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kvm_x86_ops->cache_reg(vcpu, reg);
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return vcpu->arch.regs[reg];
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}
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static inline void kvm_register_write(struct kvm_vcpu *vcpu,
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enum kvm_reg reg,
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unsigned long val)
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{
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vcpu->arch.regs[reg] = val;
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__set_bit(reg, (unsigned long *)&vcpu->arch.regs_dirty);
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__set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
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}
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static inline unsigned long kvm_rip_read(struct kvm_vcpu *vcpu)
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{
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return kvm_register_read(vcpu, VCPU_REGS_RIP);
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}
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static inline void kvm_rip_write(struct kvm_vcpu *vcpu, unsigned long val)
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{
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kvm_register_write(vcpu, VCPU_REGS_RIP, val);
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}
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static inline u64 kvm_pdptr_read(struct kvm_vcpu *vcpu, int index)
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{
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might_sleep(); /* on svm */
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if (!test_bit(VCPU_EXREG_PDPTR,
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(unsigned long *)&vcpu->arch.regs_avail))
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kvm_x86_ops->cache_reg(vcpu, (enum kvm_reg)VCPU_EXREG_PDPTR);
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return vcpu->arch.walk_mmu->pdptrs[index];
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}
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static inline ulong kvm_read_cr0_bits(struct kvm_vcpu *vcpu, ulong mask)
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{
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ulong tmask = mask & KVM_POSSIBLE_CR0_GUEST_BITS;
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if (tmask & vcpu->arch.cr0_guest_owned_bits)
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kvm_x86_ops->decache_cr0_guest_bits(vcpu);
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return vcpu->arch.cr0 & mask;
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}
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static inline ulong kvm_read_cr0(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, ~0UL);
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}
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static inline ulong kvm_read_cr4_bits(struct kvm_vcpu *vcpu, ulong mask)
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{
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ulong tmask = mask & KVM_POSSIBLE_CR4_GUEST_BITS;
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if (tmask & vcpu->arch.cr4_guest_owned_bits)
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kvm_x86_ops->decache_cr4_guest_bits(vcpu);
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return vcpu->arch.cr4 & mask;
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}
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static inline ulong kvm_read_cr3(struct kvm_vcpu *vcpu)
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{
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if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
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kvm_x86_ops->decache_cr3(vcpu);
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return vcpu->arch.cr3;
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}
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static inline ulong kvm_read_cr4(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, ~0UL);
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}
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static inline u64 kvm_read_edx_eax(struct kvm_vcpu *vcpu)
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{
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return (kvm_register_read(vcpu, VCPU_REGS_RAX) & -1u)
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| ((u64)(kvm_register_read(vcpu, VCPU_REGS_RDX) & -1u) << 32);
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}
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static inline void enter_guest_mode(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hflags |= HF_GUEST_MASK;
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}
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static inline void leave_guest_mode(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hflags &= ~HF_GUEST_MASK;
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if (vcpu->arch.load_eoi_exitmap_pending) {
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vcpu->arch.load_eoi_exitmap_pending = false;
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kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
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}
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}
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static inline bool is_guest_mode(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.hflags & HF_GUEST_MASK;
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}
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static inline bool is_smm(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.hflags & HF_SMM_MASK;
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}
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#endif
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