![Antoine Tenart](/assets/img/avatar_default.png)
Before using the PHY framework instead of the USB PHY one, we need to move the OTG state into another place, since it won't be available when USB PHY isn't used. This patch moves the OTG state into the OTG structure, and makes all the needed modifications in the drivers using the OTG state. [ balbi@ti.com : fix build regressions with phy-tahvo.c, musb_dsps.c, phy-isp1301-omap, and chipidea's debug.c ] Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
578 lines
14 KiB
C
578 lines
14 KiB
C
/*
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* MUSB OTG controller driver for Blackfin Processors
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*
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* Copyright 2006-2008 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/list.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/prefetch.h>
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#include <linux/usb/usb_phy_generic.h>
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#include <asm/cacheflush.h>
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#include "musb_core.h"
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#include "musbhsdma.h"
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#include "blackfin.h"
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struct bfin_glue {
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struct device *dev;
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struct platform_device *musb;
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struct platform_device *phy;
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};
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#define glue_to_musb(g) platform_get_drvdata(g->musb)
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/*
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* Load an endpoint's FIFO
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*/
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void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
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{
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struct musb *musb = hw_ep->musb;
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void __iomem *fifo = hw_ep->fifo;
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void __iomem *epio = hw_ep->regs;
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u8 epnum = hw_ep->epnum;
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prefetch((u8 *)src);
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musb_writew(epio, MUSB_TXCOUNT, len);
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dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
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hw_ep->epnum, fifo, len, src, epio);
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dump_fifo_data(src, len);
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if (!ANOMALY_05000380 && epnum != 0) {
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u16 dma_reg;
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flush_dcache_range((unsigned long)src,
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(unsigned long)(src + len));
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/* Setup DMA address register */
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dma_reg = (u32)src;
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
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SSYNC();
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dma_reg = (u32)src >> 16;
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
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SSYNC();
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/* Setup DMA count register */
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
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SSYNC();
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/* Enable the DMA */
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dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
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SSYNC();
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/* Wait for complete */
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while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
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cpu_relax();
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/* acknowledge dma interrupt */
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bfin_write_USB_DMA_INTERRUPT(1 << epnum);
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SSYNC();
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/* Reset DMA */
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
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SSYNC();
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} else {
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SSYNC();
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if (unlikely((unsigned long)src & 0x01))
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outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
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else
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outsw((unsigned long)fifo, src, (len + 1) >> 1);
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}
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}
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/*
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* Unload an endpoint's FIFO
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*/
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void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
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{
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struct musb *musb = hw_ep->musb;
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void __iomem *fifo = hw_ep->fifo;
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u8 epnum = hw_ep->epnum;
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if (ANOMALY_05000467 && epnum != 0) {
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u16 dma_reg;
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invalidate_dcache_range((unsigned long)dst,
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(unsigned long)(dst + len));
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/* Setup DMA address register */
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dma_reg = (u32)dst;
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
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SSYNC();
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dma_reg = (u32)dst >> 16;
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
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SSYNC();
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/* Setup DMA count register */
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
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SSYNC();
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/* Enable the DMA */
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dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
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SSYNC();
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/* Wait for complete */
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while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
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cpu_relax();
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/* acknowledge dma interrupt */
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bfin_write_USB_DMA_INTERRUPT(1 << epnum);
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SSYNC();
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/* Reset DMA */
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bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
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SSYNC();
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} else {
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SSYNC();
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/* Read the last byte of packet with odd size from address fifo + 4
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* to trigger 1 byte access to EP0 FIFO.
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*/
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if (len == 1)
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*dst = (u8)inw((unsigned long)fifo + 4);
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else {
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if (unlikely((unsigned long)dst & 0x01))
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insw_8((unsigned long)fifo, dst, len >> 1);
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else
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insw((unsigned long)fifo, dst, len >> 1);
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if (len & 0x01)
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*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
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}
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}
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dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
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'R', hw_ep->epnum, fifo, len, dst);
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dump_fifo_data(dst, len);
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}
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static irqreturn_t blackfin_interrupt(int irq, void *__hci)
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{
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unsigned long flags;
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irqreturn_t retval = IRQ_NONE;
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struct musb *musb = __hci;
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spin_lock_irqsave(&musb->lock, flags);
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musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
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musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
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musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
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if (musb->int_usb || musb->int_tx || musb->int_rx) {
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musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
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musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
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musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
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retval = musb_interrupt(musb);
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}
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/* Start sampling ID pin, when plug is removed from MUSB */
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if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
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|| musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) ||
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(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
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mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
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musb->a_wait_bcon = TIMER_DELAY;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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return retval;
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}
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static void musb_conn_timer_handler(unsigned long _musb)
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{
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struct musb *musb = (void *)_musb;
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unsigned long flags;
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u16 val;
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static u8 toggle;
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spin_lock_irqsave(&musb->lock, flags);
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switch (musb->xceiv->otg->state) {
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case OTG_STATE_A_IDLE:
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case OTG_STATE_A_WAIT_BCON:
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/* Start a new session */
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val = musb_readw(musb->mregs, MUSB_DEVCTL);
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val &= ~MUSB_DEVCTL_SESSION;
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musb_writew(musb->mregs, MUSB_DEVCTL, val);
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val |= MUSB_DEVCTL_SESSION;
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musb_writew(musb->mregs, MUSB_DEVCTL, val);
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/* Check if musb is host or peripheral. */
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val = musb_readw(musb->mregs, MUSB_DEVCTL);
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if (!(val & MUSB_DEVCTL_BDEVICE)) {
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gpio_set_value(musb->config->gpio_vrsel, 1);
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
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} else {
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gpio_set_value(musb->config->gpio_vrsel, 0);
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/* Ignore VBUSERROR and SUSPEND IRQ */
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val = musb_readb(musb->mregs, MUSB_INTRUSBE);
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val &= ~MUSB_INTR_VBUSERROR;
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musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
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val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
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musb_writeb(musb->mregs, MUSB_INTRUSB, val);
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musb->xceiv->otg->state = OTG_STATE_B_IDLE;
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}
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mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
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break;
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case OTG_STATE_B_IDLE:
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/*
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* Start a new session. It seems that MUSB needs taking
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* some time to recognize the type of the plug inserted?
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*/
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val = musb_readw(musb->mregs, MUSB_DEVCTL);
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val |= MUSB_DEVCTL_SESSION;
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musb_writew(musb->mregs, MUSB_DEVCTL, val);
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val = musb_readw(musb->mregs, MUSB_DEVCTL);
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if (!(val & MUSB_DEVCTL_BDEVICE)) {
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gpio_set_value(musb->config->gpio_vrsel, 1);
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
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} else {
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gpio_set_value(musb->config->gpio_vrsel, 0);
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/* Ignore VBUSERROR and SUSPEND IRQ */
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val = musb_readb(musb->mregs, MUSB_INTRUSBE);
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val &= ~MUSB_INTR_VBUSERROR;
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musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
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val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
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musb_writeb(musb->mregs, MUSB_INTRUSB, val);
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/* Toggle the Soft Conn bit, so that we can response to
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* the inserting of either A-plug or B-plug.
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*/
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if (toggle) {
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val = musb_readb(musb->mregs, MUSB_POWER);
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val &= ~MUSB_POWER_SOFTCONN;
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musb_writeb(musb->mregs, MUSB_POWER, val);
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toggle = 0;
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} else {
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val = musb_readb(musb->mregs, MUSB_POWER);
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val |= MUSB_POWER_SOFTCONN;
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musb_writeb(musb->mregs, MUSB_POWER, val);
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toggle = 1;
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}
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/* The delay time is set to 1/4 second by default,
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* shortening it, if accelerating A-plug detection
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* is needed in OTG mode.
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*/
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mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
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}
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break;
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default:
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dev_dbg(musb->controller, "%s state not handled\n",
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usb_otg_state_string(musb->xceiv->otg->state));
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break;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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dev_dbg(musb->controller, "state is %s\n",
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usb_otg_state_string(musb->xceiv->otg->state));
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}
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static void bfin_musb_enable(struct musb *musb)
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{
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/* REVISIT is this really correct ? */
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}
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static void bfin_musb_disable(struct musb *musb)
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{
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}
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static void bfin_musb_set_vbus(struct musb *musb, int is_on)
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{
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int value = musb->config->gpio_vrsel_active;
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if (!is_on)
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value = !value;
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gpio_set_value(musb->config->gpio_vrsel, value);
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dev_dbg(musb->controller, "VBUS %s, devctl %02x "
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/* otg %3x conf %08x prcm %08x */ "\n",
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usb_otg_state_string(musb->xceiv->otg->state),
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musb_readb(musb->mregs, MUSB_DEVCTL));
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}
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static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
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{
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return 0;
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}
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static int bfin_musb_vbus_status(struct musb *musb)
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{
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return 0;
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}
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static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
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{
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return -EIO;
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}
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static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
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u16 packet_sz, u8 *mode,
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dma_addr_t *dma_addr, u32 *len)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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/*
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* Anomaly 05000450 might cause data corruption when using DMA
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* MODE 1 transmits with short packet. So to work around this,
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* we truncate all MODE 1 transfers down to a multiple of the
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* max packet size, and then do the last short packet transfer
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* (if there is any) using MODE 0.
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*/
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if (ANOMALY_05000450) {
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if (musb_channel->transmit && *mode == 1)
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*len = *len - (*len % packet_sz);
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}
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return 0;
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}
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static void bfin_musb_reg_init(struct musb *musb)
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{
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if (ANOMALY_05000346) {
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bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
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SSYNC();
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}
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if (ANOMALY_05000347) {
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bfin_write_USB_APHY_CNTRL(0x0);
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SSYNC();
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}
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/* Configure PLL oscillator register */
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bfin_write_USB_PLLOSC_CTRL(0x3080 |
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((480/musb->config->clkin) << 1));
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SSYNC();
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bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
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SSYNC();
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bfin_write_USB_EP_NI0_RXMAXP(64);
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SSYNC();
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bfin_write_USB_EP_NI0_TXMAXP(64);
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SSYNC();
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/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
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bfin_write_USB_GLOBINTR(0x7);
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SSYNC();
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bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
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EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
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EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
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EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
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EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
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SSYNC();
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}
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static int bfin_musb_init(struct musb *musb)
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{
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/*
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* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
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* and OTG HOST modes, while rev 1.1 and greater require PE7 to
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* be low for DEVICE mode and high for HOST mode. We set it high
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* here because we are in host mode
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*/
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if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
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printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
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musb->config->gpio_vrsel);
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return -ENODEV;
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}
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gpio_direction_output(musb->config->gpio_vrsel, 0);
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musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
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if (IS_ERR_OR_NULL(musb->xceiv)) {
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gpio_free(musb->config->gpio_vrsel);
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return -EPROBE_DEFER;
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}
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bfin_musb_reg_init(musb);
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setup_timer(&musb_conn_timer, musb_conn_timer_handler,
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(unsigned long) musb);
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musb->xceiv->set_power = bfin_musb_set_power;
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musb->isr = blackfin_interrupt;
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musb->double_buffer_not_ok = true;
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return 0;
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}
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static int bfin_musb_exit(struct musb *musb)
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{
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gpio_free(musb->config->gpio_vrsel);
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usb_put_phy(musb->xceiv);
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return 0;
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}
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static const struct musb_platform_ops bfin_ops = {
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.init = bfin_musb_init,
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.exit = bfin_musb_exit,
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.enable = bfin_musb_enable,
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.disable = bfin_musb_disable,
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.set_mode = bfin_musb_set_mode,
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.vbus_status = bfin_musb_vbus_status,
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.set_vbus = bfin_musb_set_vbus,
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.adjust_channel_params = bfin_musb_adjust_channel_params,
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};
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static u64 bfin_dmamask = DMA_BIT_MASK(32);
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static int bfin_probe(struct platform_device *pdev)
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{
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struct resource musb_resources[2];
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struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct platform_device *musb;
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struct bfin_glue *glue;
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int ret = -ENOMEM;
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glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
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if (!glue)
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goto err0;
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musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
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if (!musb)
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goto err0;
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|
|
|
musb->dev.parent = &pdev->dev;
|
|
musb->dev.dma_mask = &bfin_dmamask;
|
|
musb->dev.coherent_dma_mask = bfin_dmamask;
|
|
|
|
glue->dev = &pdev->dev;
|
|
glue->musb = musb;
|
|
|
|
pdata->platform_ops = &bfin_ops;
|
|
|
|
glue->phy = usb_phy_generic_register();
|
|
if (IS_ERR(glue->phy))
|
|
goto err1;
|
|
platform_set_drvdata(pdev, glue);
|
|
|
|
memset(musb_resources, 0x00, sizeof(*musb_resources) *
|
|
ARRAY_SIZE(musb_resources));
|
|
|
|
musb_resources[0].name = pdev->resource[0].name;
|
|
musb_resources[0].start = pdev->resource[0].start;
|
|
musb_resources[0].end = pdev->resource[0].end;
|
|
musb_resources[0].flags = pdev->resource[0].flags;
|
|
|
|
musb_resources[1].name = pdev->resource[1].name;
|
|
musb_resources[1].start = pdev->resource[1].start;
|
|
musb_resources[1].end = pdev->resource[1].end;
|
|
musb_resources[1].flags = pdev->resource[1].flags;
|
|
|
|
ret = platform_device_add_resources(musb, musb_resources,
|
|
ARRAY_SIZE(musb_resources));
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to add resources\n");
|
|
goto err2;
|
|
}
|
|
|
|
ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to add platform_data\n");
|
|
goto err2;
|
|
}
|
|
|
|
ret = platform_device_add(musb);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to register musb device\n");
|
|
goto err2;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
usb_phy_generic_unregister(glue->phy);
|
|
|
|
err1:
|
|
platform_device_put(musb);
|
|
|
|
err0:
|
|
return ret;
|
|
}
|
|
|
|
static int bfin_remove(struct platform_device *pdev)
|
|
{
|
|
struct bfin_glue *glue = platform_get_drvdata(pdev);
|
|
|
|
platform_device_unregister(glue->musb);
|
|
usb_phy_generic_unregister(glue->phy);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int bfin_suspend(struct device *dev)
|
|
{
|
|
struct bfin_glue *glue = dev_get_drvdata(dev);
|
|
struct musb *musb = glue_to_musb(glue);
|
|
|
|
if (is_host_active(musb))
|
|
/*
|
|
* During hibernate gpio_vrsel will change from high to low
|
|
* low which will generate wakeup event resume the system
|
|
* immediately. Set it to 0 before hibernate to avoid this
|
|
* wakeup event.
|
|
*/
|
|
gpio_set_value(musb->config->gpio_vrsel, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bfin_resume(struct device *dev)
|
|
{
|
|
struct bfin_glue *glue = dev_get_drvdata(dev);
|
|
struct musb *musb = glue_to_musb(glue);
|
|
|
|
bfin_musb_reg_init(musb);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
|
|
|
|
static struct platform_driver bfin_driver = {
|
|
.probe = bfin_probe,
|
|
.remove = __exit_p(bfin_remove),
|
|
.driver = {
|
|
.name = "musb-blackfin",
|
|
.pm = &bfin_pm_ops,
|
|
},
|
|
};
|
|
|
|
MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
|
|
MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
|
|
MODULE_LICENSE("GPL v2");
|
|
module_platform_driver(bfin_driver);
|