![Stephen Hemminger](/assets/img/avatar_default.png)
Occasionally the system gets into a state where the CMOS clock has gotten slightly ahead of current time and the periodic update of RTC fails. The message is a nuisance and repeats spamming the log. See: http://www.ntp.org/ntpfaq/NTP-s-trbl-spec.htm#Q-LINUX-SET-RTC-MMSS Rather than just removing the message, make it show only once and reduce severity since it indicates a normal and non urgent condition. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Matt Turner <mattst88@gmail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Howells <dhowells@redhat.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
528 lines
14 KiB
C
528 lines
14 KiB
C
/*
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* linux/arch/alpha/kernel/time.c
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*
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* Copyright (C) 1991, 1992, 1995, 1999, 2000 Linus Torvalds
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*
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* This file contains the PC-specific time handling details:
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* reading the RTC at bootup, etc..
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* 1994-07-02 Alan Modra
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* fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
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* 1995-03-26 Markus Kuhn
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* fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
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* precision CMOS clock update
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* 1997-09-10 Updated NTP code according to technical memorandum Jan '96
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* "A Kernel Model for Precision Timekeeping" by Dave Mills
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* 1997-01-09 Adrian Sun
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* use interval timer if CONFIG_RTC=y
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* 1997-10-29 John Bowman (bowman@math.ualberta.ca)
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* fixed tick loss calculation in timer_interrupt
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* (round system clock to nearest tick instead of truncating)
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* fixed algorithm in time_init for getting time from CMOS clock
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* 1999-04-16 Thorsten Kranzkowski (dl8bcu@gmx.net)
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* fixed algorithm in do_gettimeofday() for calculating the precise time
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* from processor cycle counter (now taking lost_ticks into account)
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* 2000-08-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
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* Fixed time_init to be aware of epoches != 1900. This prevents
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* booting up in 2048 for me;) Code is stolen from rtc.c.
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* 2003-06-03 R. Scott Bailey <scott.bailey@eds.com>
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* Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
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*/
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/bcd.h>
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#include <linux/profile.h>
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#include <linux/irq_work.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/hwrpb.h>
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#include <asm/8253pit.h>
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#include <asm/rtc.h>
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#include <linux/mc146818rtc.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/clocksource.h>
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#include "proto.h"
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#include "irq_impl.h"
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static int set_rtc_mmss(unsigned long);
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DEFINE_SPINLOCK(rtc_lock);
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EXPORT_SYMBOL(rtc_lock);
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#define TICK_SIZE (tick_nsec / 1000)
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/*
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* Shift amount by which scaled_ticks_per_cycle is scaled. Shifting
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* by 48 gives us 16 bits for HZ while keeping the accuracy good even
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* for large CPU clock rates.
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*/
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#define FIX_SHIFT 48
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/* lump static variables together for more efficient access: */
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static struct {
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/* cycle counter last time it got invoked */
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__u32 last_time;
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/* ticks/cycle * 2^48 */
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unsigned long scaled_ticks_per_cycle;
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/* partial unused tick */
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unsigned long partial_tick;
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} state;
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unsigned long est_cycle_freq;
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#ifdef CONFIG_IRQ_WORK
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DEFINE_PER_CPU(u8, irq_work_pending);
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#define set_irq_work_pending_flag() __get_cpu_var(irq_work_pending) = 1
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#define test_irq_work_pending() __get_cpu_var(irq_work_pending)
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#define clear_irq_work_pending() __get_cpu_var(irq_work_pending) = 0
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void set_irq_work_pending(void)
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{
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set_irq_work_pending_flag();
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}
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#else /* CONFIG_IRQ_WORK */
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#define test_irq_work_pending() 0
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#define clear_irq_work_pending()
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#endif /* CONFIG_IRQ_WORK */
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static inline __u32 rpcc(void)
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{
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__u32 result;
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asm volatile ("rpcc %0" : "=r"(result));
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return result;
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}
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int update_persistent_clock(struct timespec now)
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{
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return set_rtc_mmss(now.tv_sec);
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}
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void read_persistent_clock(struct timespec *ts)
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{
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unsigned int year, mon, day, hour, min, sec, epoch;
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sec = CMOS_READ(RTC_SECONDS);
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min = CMOS_READ(RTC_MINUTES);
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hour = CMOS_READ(RTC_HOURS);
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day = CMOS_READ(RTC_DAY_OF_MONTH);
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mon = CMOS_READ(RTC_MONTH);
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year = CMOS_READ(RTC_YEAR);
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if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
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sec = bcd2bin(sec);
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min = bcd2bin(min);
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hour = bcd2bin(hour);
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day = bcd2bin(day);
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mon = bcd2bin(mon);
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year = bcd2bin(year);
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}
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/* PC-like is standard; used for year >= 70 */
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epoch = 1900;
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if (year < 20)
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epoch = 2000;
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else if (year >= 20 && year < 48)
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/* NT epoch */
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epoch = 1980;
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else if (year >= 48 && year < 70)
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/* Digital UNIX epoch */
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epoch = 1952;
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printk(KERN_INFO "Using epoch = %d\n", epoch);
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if ((year += epoch) < 1970)
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year += 100;
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ts->tv_sec = mktime(year, mon, day, hour, min, sec);
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}
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "do_timer()" routine every clocktick
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*/
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irqreturn_t timer_interrupt(int irq, void *dev)
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{
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unsigned long delta;
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__u32 now;
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long nticks;
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#ifndef CONFIG_SMP
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/* Not SMP, do kernel PC profiling here. */
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profile_tick(CPU_PROFILING);
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#endif
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write_seqlock(&xtime_lock);
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/*
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* Calculate how many ticks have passed since the last update,
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* including any previous partial leftover. Save any resulting
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* fraction for the next pass.
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*/
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now = rpcc();
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delta = now - state.last_time;
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state.last_time = now;
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delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
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state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
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nticks = delta >> FIX_SHIFT;
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if (nticks)
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do_timer(nticks);
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write_sequnlock(&xtime_lock);
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if (test_irq_work_pending()) {
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clear_irq_work_pending();
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irq_work_run();
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}
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#ifndef CONFIG_SMP
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while (nticks--)
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update_process_times(user_mode(get_irq_regs()));
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#endif
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return IRQ_HANDLED;
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}
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void __init
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common_init_rtc(void)
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{
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unsigned char x;
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/* Reset periodic interrupt frequency. */
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x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
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/* Test includes known working values on various platforms
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where 0x26 is wrong; we refuse to change those. */
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if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
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printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
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CMOS_WRITE(0x26, RTC_FREQ_SELECT);
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}
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/* Turn on periodic interrupts. */
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x = CMOS_READ(RTC_CONTROL);
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if (!(x & RTC_PIE)) {
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printk("Turning on RTC interrupts.\n");
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x |= RTC_PIE;
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x &= ~(RTC_AIE | RTC_UIE);
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CMOS_WRITE(x, RTC_CONTROL);
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}
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(void) CMOS_READ(RTC_INTR_FLAGS);
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outb(0x36, 0x43); /* pit counter 0: system timer */
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outb(0x00, 0x40);
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outb(0x00, 0x40);
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outb(0xb6, 0x43); /* pit counter 2: speaker */
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outb(0x31, 0x42);
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outb(0x13, 0x42);
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init_rtc_irq();
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}
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unsigned int common_get_rtc_time(struct rtc_time *time)
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{
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return __get_rtc_time(time);
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}
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int common_set_rtc_time(struct rtc_time *time)
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{
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return __set_rtc_time(time);
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}
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/* Validate a computed cycle counter result against the known bounds for
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the given processor core. There's too much brokenness in the way of
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timing hardware for any one method to work everywhere. :-(
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Return 0 if the result cannot be trusted, otherwise return the argument. */
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static unsigned long __init
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validate_cc_value(unsigned long cc)
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{
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static struct bounds {
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unsigned int min, max;
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} cpu_hz[] __initdata = {
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[EV3_CPU] = { 50000000, 200000000 }, /* guess */
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[EV4_CPU] = { 100000000, 300000000 },
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[LCA4_CPU] = { 100000000, 300000000 }, /* guess */
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[EV45_CPU] = { 200000000, 300000000 },
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[EV5_CPU] = { 250000000, 433000000 },
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[EV56_CPU] = { 333000000, 667000000 },
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[PCA56_CPU] = { 400000000, 600000000 }, /* guess */
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[PCA57_CPU] = { 500000000, 600000000 }, /* guess */
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[EV6_CPU] = { 466000000, 600000000 },
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[EV67_CPU] = { 600000000, 750000000 },
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[EV68AL_CPU] = { 750000000, 940000000 },
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[EV68CB_CPU] = { 1000000000, 1333333333 },
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/* None of the following are shipping as of 2001-11-01. */
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[EV68CX_CPU] = { 1000000000, 1700000000 }, /* guess */
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[EV69_CPU] = { 1000000000, 1700000000 }, /* guess */
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[EV7_CPU] = { 800000000, 1400000000 }, /* guess */
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[EV79_CPU] = { 1000000000, 2000000000 }, /* guess */
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};
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/* Allow for some drift in the crystal. 10MHz is more than enough. */
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const unsigned int deviation = 10000000;
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struct percpu_struct *cpu;
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unsigned int index;
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cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
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index = cpu->type & 0xffffffff;
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/* If index out of bounds, no way to validate. */
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if (index >= ARRAY_SIZE(cpu_hz))
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return cc;
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/* If index contains no data, no way to validate. */
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if (cpu_hz[index].max == 0)
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return cc;
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if (cc < cpu_hz[index].min - deviation
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|| cc > cpu_hz[index].max + deviation)
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return 0;
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return cc;
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}
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/*
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* Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
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* arch/i386/time.c.
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*/
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#define CALIBRATE_LATCH 0xffff
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#define TIMEOUT_COUNT 0x100000
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static unsigned long __init
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calibrate_cc_with_pit(void)
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{
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int cc, count = 0;
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/* Set the Gate high, disable speaker */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/*
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* Now let's take care of CTC channel 2
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*
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* Set the Gate high, program CTC channel 2 for mode 0,
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* (interrupt on terminal count mode), binary count,
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* load 5 * LATCH count, (LSB and MSB) to begin countdown.
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*/
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outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
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outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
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outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
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cc = rpcc();
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do {
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count++;
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} while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
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cc = rpcc() - cc;
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/* Error: ECTCNEVERSET or ECPUTOOFAST. */
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if (count <= 1 || count == TIMEOUT_COUNT)
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return 0;
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return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
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}
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/* The Linux interpretation of the CMOS clock register contents:
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When the Update-In-Progress (UIP) flag goes from 1 to 0, the
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RTC registers show the second which has precisely just started.
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Let's hope other operating systems interpret the RTC the same way. */
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static unsigned long __init
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rpcc_after_update_in_progress(void)
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{
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do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
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do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
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return rpcc();
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}
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#ifndef CONFIG_SMP
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/* Until and unless we figure out how to get cpu cycle counters
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in sync and keep them there, we can't use the rpcc. */
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static cycle_t read_rpcc(struct clocksource *cs)
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{
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cycle_t ret = (cycle_t)rpcc();
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return ret;
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}
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static struct clocksource clocksource_rpcc = {
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.name = "rpcc",
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.rating = 300,
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.read = read_rpcc,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS
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};
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static inline void register_rpcc_clocksource(long cycle_freq)
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{
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clocksource_calc_mult_shift(&clocksource_rpcc, cycle_freq, 4);
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clocksource_register(&clocksource_rpcc);
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}
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#else /* !CONFIG_SMP */
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static inline void register_rpcc_clocksource(long cycle_freq)
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{
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}
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#endif /* !CONFIG_SMP */
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void __init
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time_init(void)
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{
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unsigned int cc1, cc2;
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unsigned long cycle_freq, tolerance;
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long diff;
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/* Calibrate CPU clock -- attempt #1. */
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if (!est_cycle_freq)
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est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
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cc1 = rpcc();
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/* Calibrate CPU clock -- attempt #2. */
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if (!est_cycle_freq) {
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cc1 = rpcc_after_update_in_progress();
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cc2 = rpcc_after_update_in_progress();
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est_cycle_freq = validate_cc_value(cc2 - cc1);
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cc1 = cc2;
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}
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cycle_freq = hwrpb->cycle_freq;
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if (est_cycle_freq) {
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/* If the given value is within 250 PPM of what we calculated,
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accept it. Otherwise, use what we found. */
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tolerance = cycle_freq / 4000;
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diff = cycle_freq - est_cycle_freq;
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if (diff < 0)
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diff = -diff;
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if ((unsigned long)diff > tolerance) {
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cycle_freq = est_cycle_freq;
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printk("HWRPB cycle frequency bogus. "
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"Estimated %lu Hz\n", cycle_freq);
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} else {
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est_cycle_freq = 0;
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}
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} else if (! validate_cc_value (cycle_freq)) {
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printk("HWRPB cycle frequency bogus, "
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"and unable to estimate a proper value!\n");
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}
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/* From John Bowman <bowman@math.ualberta.ca>: allow the values
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to settle, as the Update-In-Progress bit going low isn't good
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enough on some hardware. 2ms is our guess; we haven't found
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bogomips yet, but this is close on a 500Mhz box. */
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__delay(1000000);
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if (HZ > (1<<16)) {
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extern void __you_loose (void);
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__you_loose();
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}
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register_rpcc_clocksource(cycle_freq);
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state.last_time = cc1;
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state.scaled_ticks_per_cycle
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= ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
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state.partial_tick = 0L;
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/* Startup the timer source. */
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alpha_mv.init_rtc();
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}
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/*
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* In order to set the CMOS clock precisely, set_rtc_mmss has to be
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* called 500 ms after the second nowtime has started, because when
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* nowtime is written into the registers of the CMOS clock, it will
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* jump to the next second precisely 500 ms later. Check the Motorola
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* MC146818A or Dallas DS12887 data sheet for details.
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*
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* BUG: This routine does not handle hour overflow properly; it just
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* sets the minutes. Usually you won't notice until after reboot!
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*/
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static int
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set_rtc_mmss(unsigned long nowtime)
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{
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int retval = 0;
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int real_seconds, real_minutes, cmos_minutes;
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unsigned char save_control, save_freq_select;
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/* irq are locally disabled here */
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spin_lock(&rtc_lock);
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/* Tell the clock it's being set */
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save_control = CMOS_READ(RTC_CONTROL);
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CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
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/* Stop and reset prescaler */
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save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
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CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
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cmos_minutes = CMOS_READ(RTC_MINUTES);
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if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
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cmos_minutes = bcd2bin(cmos_minutes);
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/*
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* since we're only adjusting minutes and seconds,
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* don't interfere with hour overflow. This avoids
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* messing with unknown time zones but requires your
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* RTC not to be off by more than 15 minutes
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*/
|
|
real_seconds = nowtime % 60;
|
|
real_minutes = nowtime / 60;
|
|
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
|
|
/* correct for half hour time zone */
|
|
real_minutes += 30;
|
|
}
|
|
real_minutes %= 60;
|
|
|
|
if (abs(real_minutes - cmos_minutes) < 30) {
|
|
if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
|
|
real_seconds = bin2bcd(real_seconds);
|
|
real_minutes = bin2bcd(real_minutes);
|
|
}
|
|
CMOS_WRITE(real_seconds,RTC_SECONDS);
|
|
CMOS_WRITE(real_minutes,RTC_MINUTES);
|
|
} else {
|
|
printk_once(KERN_NOTICE
|
|
"set_rtc_mmss: can't update from %d to %d\n",
|
|
cmos_minutes, real_minutes);
|
|
retval = -1;
|
|
}
|
|
|
|
/* The following flags have to be released exactly in this order,
|
|
* otherwise the DS12887 (popular MC146818A clone with integrated
|
|
* battery and quartz) will not reset the oscillator and will not
|
|
* update precisely 500 ms later. You won't find this mentioned in
|
|
* the Dallas Semiconductor data sheets, but who believes data
|
|
* sheets anyway ... -- Markus Kuhn
|
|
*/
|
|
CMOS_WRITE(save_control, RTC_CONTROL);
|
|
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
|
|
spin_unlock(&rtc_lock);
|
|
|
|
return retval;
|
|
}
|