![Graf Yang](/assets/img/avatar_default.png)
This allows things to be shared between the different watchdog sources. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
300 lines
5.9 KiB
C
300 lines
5.9 KiB
C
/*
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* Blackfin nmi_watchdog Driver
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*
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* Originally based on bfin_wdt.c
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* Copyright 2010-2010 Analog Devices Inc.
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* Graff Yang <graf.yang@analog.com>
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/bitops.h>
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#include <linux/hardirq.h>
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#include <linux/sysdev.h>
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#include <linux/pm.h>
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#include <linux/nmi.h>
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#include <linux/smp.h>
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#include <linux/timer.h>
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#include <asm/blackfin.h>
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#include <asm/atomic.h>
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#include <asm/cacheflush.h>
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#include <asm/bfin_watchdog.h>
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#define DRV_NAME "nmi-wdt"
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#define NMI_WDT_TIMEOUT 5 /* 5 seconds */
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#define NMI_CHECK_TIMEOUT (4 * HZ) /* 4 seconds in jiffies */
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static int nmi_wdt_cpu = 1;
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static unsigned int timeout = NMI_WDT_TIMEOUT;
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static int nmi_active;
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static unsigned short wdoga_ctl;
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static unsigned int wdoga_cnt;
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static struct corelock_slot saved_corelock;
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static atomic_t nmi_touched[NR_CPUS];
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static struct timer_list ntimer;
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enum {
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COREA_ENTER_NMI = 0,
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COREA_EXIT_NMI,
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COREB_EXIT_NMI,
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NMI_EVENT_NR,
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};
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static unsigned long nmi_event __attribute__ ((__section__(".l2.bss")));
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/* we are in nmi, non-atomic bit ops is safe */
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static inline void set_nmi_event(int event)
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{
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__set_bit(event, &nmi_event);
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}
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static inline void wait_nmi_event(int event)
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{
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while (!test_bit(event, &nmi_event))
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barrier();
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__clear_bit(event, &nmi_event);
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}
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static inline void send_corea_nmi(void)
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{
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wdoga_ctl = bfin_read_WDOGA_CTL();
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wdoga_cnt = bfin_read_WDOGA_CNT();
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bfin_write_WDOGA_CTL(WDEN_DISABLE);
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bfin_write_WDOGA_CNT(0);
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bfin_write_WDOGA_CTL(WDEN_ENABLE | ICTL_NMI);
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}
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static inline void restore_corea_nmi(void)
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{
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bfin_write_WDOGA_CTL(WDEN_DISABLE);
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bfin_write_WDOGA_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
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bfin_write_WDOGA_CNT(wdoga_cnt);
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bfin_write_WDOGA_CTL(wdoga_ctl);
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}
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static inline void save_corelock(void)
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{
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saved_corelock = corelock;
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corelock.lock = 0;
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}
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static inline void restore_corelock(void)
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{
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corelock = saved_corelock;
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}
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static inline void nmi_wdt_keepalive(void)
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{
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bfin_write_WDOGB_STAT(0);
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}
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static inline void nmi_wdt_stop(void)
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{
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bfin_write_WDOGB_CTL(WDEN_DISABLE);
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}
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/* before calling this function, you must stop the WDT */
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static inline void nmi_wdt_clear(void)
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{
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/* clear TRO bit, disable event generation */
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bfin_write_WDOGB_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
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}
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static inline void nmi_wdt_start(void)
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{
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bfin_write_WDOGB_CTL(WDEN_ENABLE | ICTL_NMI);
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}
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static inline int nmi_wdt_running(void)
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{
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return ((bfin_read_WDOGB_CTL() & WDEN_MASK) != WDEN_DISABLE);
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}
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static inline int nmi_wdt_set_timeout(unsigned long t)
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{
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u32 cnt, max_t, sclk;
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int run;
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sclk = get_sclk();
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max_t = -1 / sclk;
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cnt = t * sclk;
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if (t > max_t) {
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pr_warning("NMI: timeout value is too large\n");
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return -EINVAL;
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}
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run = nmi_wdt_running();
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nmi_wdt_stop();
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bfin_write_WDOGB_CNT(cnt);
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if (run)
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nmi_wdt_start();
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timeout = t;
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return 0;
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}
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int check_nmi_wdt_touched(void)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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cpumask_t mask = cpu_online_map;
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if (!atomic_read(&nmi_touched[this_cpu]))
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return 0;
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atomic_set(&nmi_touched[this_cpu], 0);
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cpu_clear(this_cpu, mask);
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for_each_cpu_mask(cpu, mask) {
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invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]),
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(unsigned long)(&nmi_touched[cpu]));
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if (!atomic_read(&nmi_touched[cpu]))
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return 0;
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atomic_set(&nmi_touched[cpu], 0);
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}
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return 1;
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}
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static void nmi_wdt_timer(unsigned long data)
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{
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if (check_nmi_wdt_touched())
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nmi_wdt_keepalive();
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mod_timer(&ntimer, jiffies + NMI_CHECK_TIMEOUT);
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}
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static int __init init_nmi_wdt(void)
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{
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nmi_wdt_set_timeout(timeout);
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nmi_wdt_start();
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nmi_active = true;
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init_timer(&ntimer);
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ntimer.function = nmi_wdt_timer;
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ntimer.expires = jiffies + NMI_CHECK_TIMEOUT;
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add_timer(&ntimer);
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pr_info("nmi_wdt: initialized: timeout=%d sec\n", timeout);
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return 0;
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}
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device_initcall(init_nmi_wdt);
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void touch_nmi_watchdog(void)
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{
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atomic_set(&nmi_touched[smp_processor_id()], 1);
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}
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/* Suspend/resume support */
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#ifdef CONFIG_PM
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static int nmi_wdt_suspend(struct sys_device *dev, pm_message_t state)
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{
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nmi_wdt_stop();
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return 0;
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}
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static int nmi_wdt_resume(struct sys_device *dev)
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{
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if (nmi_active)
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nmi_wdt_start();
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return 0;
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}
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static struct sysdev_class nmi_sysclass = {
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.name = DRV_NAME,
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.resume = nmi_wdt_resume,
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.suspend = nmi_wdt_suspend,
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};
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static struct sys_device device_nmi_wdt = {
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.id = 0,
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.cls = &nmi_sysclass,
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};
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static int __init init_nmi_wdt_sysfs(void)
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{
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int error;
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if (!nmi_active)
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return 0;
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error = sysdev_class_register(&nmi_sysclass);
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if (!error)
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error = sysdev_register(&device_nmi_wdt);
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return error;
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}
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late_initcall(init_nmi_wdt_sysfs);
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#endif /* CONFIG_PM */
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asmlinkage notrace void do_nmi(struct pt_regs *fp)
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{
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unsigned int cpu = smp_processor_id();
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nmi_enter();
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cpu_pda[cpu].__nmi_count += 1;
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if (cpu == nmi_wdt_cpu) {
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/* CoreB goes here first */
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/* reload the WDOG_STAT */
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nmi_wdt_keepalive();
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/* clear nmi interrupt for CoreB */
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nmi_wdt_stop();
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nmi_wdt_clear();
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/* trigger NMI interrupt of CoreA */
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send_corea_nmi();
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/* waiting CoreB to enter NMI */
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wait_nmi_event(COREA_ENTER_NMI);
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/* recover WDOGA's settings */
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restore_corea_nmi();
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save_corelock();
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/* corelock is save/cleared, CoreA is dummping messages */
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wait_nmi_event(COREA_EXIT_NMI);
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} else {
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/* OK, CoreA entered NMI */
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set_nmi_event(COREA_ENTER_NMI);
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}
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pr_emerg("\nNMI Watchdog detected LOCKUP, dump for CPU %d\n", cpu);
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dump_bfin_process(fp);
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dump_bfin_mem(fp);
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show_regs(fp);
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dump_bfin_trace_buffer();
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show_stack(current, (unsigned long *)fp);
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if (cpu == nmi_wdt_cpu) {
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pr_emerg("This fault is not recoverable, sorry!\n");
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/* CoreA dump finished, restore the corelock */
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restore_corelock();
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set_nmi_event(COREB_EXIT_NMI);
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} else {
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/* CoreB dump finished, notice the CoreA we are done */
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set_nmi_event(COREA_EXIT_NMI);
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/* synchronize with CoreA */
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wait_nmi_event(COREB_EXIT_NMI);
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}
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nmi_exit();
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}
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