![Octavian Purdila](/assets/img/avatar_default.png)
For ppc750 processors which use 4 performance counters instead of the 6 G4 uses but otherwise is compatible with G4. Signed-off-by: Octavian Purdila <opurdila@ixiacom.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
214 lines
5.3 KiB
C
214 lines
5.3 KiB
C
/*
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* arch/powerpc/oprofile/op_model_7450.c
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*
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* Freescale 745x/744x oprofile support, based on fsl_booke support
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* Copyright (c) 2004 Freescale Semiconductor, Inc
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*
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* Author: Andy Fleming
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* Maintainer: Kumar Gala <galak@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/oprofile.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/page.h>
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#include <asm/pmc.h>
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#include <asm/oprofile_impl.h>
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static unsigned long reset_value[OP_MAX_COUNTER];
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static int oprofile_running;
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static u32 mmcr0_val, mmcr1_val, mmcr2_val, num_pmcs;
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#define MMCR0_PMC1_SHIFT 6
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#define MMCR0_PMC2_SHIFT 0
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#define MMCR1_PMC3_SHIFT 27
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#define MMCR1_PMC4_SHIFT 22
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#define MMCR1_PMC5_SHIFT 17
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#define MMCR1_PMC6_SHIFT 11
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#define mmcr0_event1(event) \
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((event << MMCR0_PMC1_SHIFT) & MMCR0_PMC1SEL)
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#define mmcr0_event2(event) \
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((event << MMCR0_PMC2_SHIFT) & MMCR0_PMC2SEL)
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#define mmcr1_event3(event) \
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((event << MMCR1_PMC3_SHIFT) & MMCR1_PMC3SEL)
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#define mmcr1_event4(event) \
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((event << MMCR1_PMC4_SHIFT) & MMCR1_PMC4SEL)
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#define mmcr1_event5(event) \
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((event << MMCR1_PMC5_SHIFT) & MMCR1_PMC5SEL)
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#define mmcr1_event6(event) \
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((event << MMCR1_PMC6_SHIFT) & MMCR1_PMC6SEL)
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#define MMCR0_INIT (MMCR0_FC | MMCR0_FCS | MMCR0_FCP | MMCR0_FCM1 | MMCR0_FCM0)
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/* Unfreezes the counters on this CPU, enables the interrupt,
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* enables the counters to trigger the interrupt, and sets the
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* counters to only count when the mark bit is not set.
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*/
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static void pmc_start_ctrs(void)
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{
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u32 mmcr0 = mfspr(SPRN_MMCR0);
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mmcr0 &= ~(MMCR0_FC | MMCR0_FCM0);
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mmcr0 |= (MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);
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mtspr(SPRN_MMCR0, mmcr0);
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}
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/* Disables the counters on this CPU, and freezes them */
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static void pmc_stop_ctrs(void)
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{
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u32 mmcr0 = mfspr(SPRN_MMCR0);
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mmcr0 |= MMCR0_FC;
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mmcr0 &= ~(MMCR0_FCECE | MMCR0_PMC1CE | MMCR0_PMCnCE | MMCR0_PMXE);
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mtspr(SPRN_MMCR0, mmcr0);
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}
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/* Configures the counters on this CPU based on the global
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* settings */
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static int fsl7450_cpu_setup(struct op_counter_config *ctr)
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{
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/* freeze all counters */
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pmc_stop_ctrs();
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mtspr(SPRN_MMCR0, mmcr0_val);
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mtspr(SPRN_MMCR1, mmcr1_val);
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if (num_pmcs > 4)
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mtspr(SPRN_MMCR2, mmcr2_val);
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return 0;
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}
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/* Configures the global settings for the countes on all CPUs. */
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static int fsl7450_reg_setup(struct op_counter_config *ctr,
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struct op_system_config *sys,
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int num_ctrs)
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{
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int i;
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num_pmcs = num_ctrs;
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/* Our counters count up, and "count" refers to
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* how much before the next interrupt, and we interrupt
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* on overflow. So we calculate the starting value
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* which will give us "count" until overflow.
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* Then we set the events on the enabled counters */
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for (i = 0; i < num_ctrs; ++i)
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reset_value[i] = 0x80000000UL - ctr[i].count;
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/* Set events for Counters 1 & 2 */
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mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event)
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| mmcr0_event2(ctr[1].event);
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/* Setup user/kernel bits */
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if (sys->enable_kernel)
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mmcr0_val &= ~(MMCR0_FCS);
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if (sys->enable_user)
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mmcr0_val &= ~(MMCR0_FCP);
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/* Set events for Counters 3-6 */
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mmcr1_val = mmcr1_event3(ctr[2].event)
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| mmcr1_event4(ctr[3].event);
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if (num_ctrs > 4)
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mmcr1_val |= mmcr1_event5(ctr[4].event)
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| mmcr1_event6(ctr[5].event);
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mmcr2_val = 0;
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return 0;
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}
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/* Sets the counters on this CPU to the chosen values, and starts them */
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static int fsl7450_start(struct op_counter_config *ctr)
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{
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int i;
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mtmsr(mfmsr() | MSR_PMM);
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for (i = 0; i < num_pmcs; ++i) {
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if (ctr[i].enabled)
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classic_ctr_write(i, reset_value[i]);
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else
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classic_ctr_write(i, 0);
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}
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/* Clear the freeze bit, and enable the interrupt.
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* The counters won't actually start until the rfi clears
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* the PMM bit */
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pmc_start_ctrs();
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oprofile_running = 1;
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return 0;
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}
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/* Stop the counters on this CPU */
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static void fsl7450_stop(void)
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{
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/* freeze counters */
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pmc_stop_ctrs();
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oprofile_running = 0;
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mb();
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}
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/* Handle the interrupt on this CPU, and log a sample for each
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* event that triggered the interrupt */
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static void fsl7450_handle_interrupt(struct pt_regs *regs,
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struct op_counter_config *ctr)
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{
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unsigned long pc;
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int is_kernel;
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int val;
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int i;
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/* set the PMM bit (see comment below) */
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mtmsr(mfmsr() | MSR_PMM);
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pc = mfspr(SPRN_SIAR);
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is_kernel = is_kernel_addr(pc);
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for (i = 0; i < num_pmcs; ++i) {
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val = classic_ctr_read(i);
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if (val < 0) {
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if (oprofile_running && ctr[i].enabled) {
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oprofile_add_ext_sample(pc, regs, i, is_kernel);
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classic_ctr_write(i, reset_value[i]);
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} else {
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classic_ctr_write(i, 0);
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}
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}
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}
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/* The freeze bit was set by the interrupt. */
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/* Clear the freeze bit, and reenable the interrupt.
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* The counters won't actually start until the rfi clears
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* the PM/M bit */
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pmc_start_ctrs();
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}
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struct op_powerpc_model op_model_7450= {
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.reg_setup = fsl7450_reg_setup,
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.cpu_setup = fsl7450_cpu_setup,
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.start = fsl7450_start,
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.stop = fsl7450_stop,
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.handle_interrupt = fsl7450_handle_interrupt,
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};
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