32321e950d
On Micron and Numonyx devices, the status register write command (WRSR), raises a work-in-progress bit (WIP) on the status register. The datasheets for these devices specify that while the status register write is in progress, the status register WIP bit can still be read to check the end of the operation. This commit adds a wait_till_ready call on lock/unlock operations, which is required for Micron and Numonyx but should be harmless for others. This is needed to prevent applications from issuing erase or program operations before the unlock operation is completed. Reported-by: Stas Sergeev <stsp@list.ru> Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
1421 lines
40 KiB
C
1421 lines
40 KiB
C
/*
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* Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
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* influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
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*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/math64.h>
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#include <linux/sizes.h>
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#include <linux/mtd/mtd.h>
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#include <linux/of_platform.h>
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#include <linux/spi/flash.h>
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#include <linux/mtd/spi-nor.h>
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/* Define max times to check status register before we give up. */
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/*
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* For everything but full-chip erase; probably could be much smaller, but kept
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* around for safety for now
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*/
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#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
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/*
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* For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
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* for larger flash
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*/
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#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
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#define SPI_NOR_MAX_ID_LEN 6
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#define SPI_NOR_MAX_ADDR_WIDTH 4
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struct flash_info {
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char *name;
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/*
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* This array stores the ID bytes.
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* The first three bytes are the JEDIC ID.
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* JEDEC ID zero means "no ID" (mostly older chips).
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*/
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u8 id[SPI_NOR_MAX_ID_LEN];
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u8 id_len;
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/* The size listed here is what works with SPINOR_OP_SE, which isn't
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* necessarily called a "sector" by the vendor.
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*/
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unsigned sector_size;
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u16 n_sectors;
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u16 page_size;
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u16 addr_width;
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u16 flags;
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#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
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#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
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#define SST_WRITE 0x04 /* use SST byte programming */
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#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
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#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
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#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
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#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
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#define USE_FSR 0x80 /* use flag status register */
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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static const struct flash_info *spi_nor_match_id(const char *name);
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/*
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* Read the status register, returning its value in the location
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* Return the status register value.
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* Returns negative if error occurred.
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*/
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static int read_sr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
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if (ret < 0) {
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pr_err("error %d reading SR\n", (int) ret);
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return ret;
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}
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return val;
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}
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/*
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* Read the flag status register, returning its value in the location
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* Return the status register value.
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* Returns negative if error occurred.
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*/
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static int read_fsr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
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if (ret < 0) {
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pr_err("error %d reading FSR\n", ret);
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return ret;
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}
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return val;
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}
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/*
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* Read configuration register, returning its value in the
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* location. Return the configuration register value.
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* Returns negative if error occured.
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*/
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static int read_cr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading CR\n", ret);
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return ret;
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}
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return val;
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}
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/*
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* Dummy Cycle calculation for different type of read.
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* It can be used to support more commands with
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* different dummy cycle requirements.
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*/
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static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
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{
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switch (nor->flash_read) {
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case SPI_NOR_FAST:
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case SPI_NOR_DUAL:
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case SPI_NOR_QUAD:
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return 8;
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case SPI_NOR_NORMAL:
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return 0;
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}
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return 0;
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}
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/*
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* Write status register 1 byte
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* Returns negative if error occurred.
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*/
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static inline int write_sr(struct spi_nor *nor, u8 val)
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{
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nor->cmd_buf[0] = val;
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return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
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}
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/*
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* Set write enable latch with Write Enable command.
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* Returns negative if error occurred.
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*/
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static inline int write_enable(struct spi_nor *nor)
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{
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return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
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}
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/*
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* Send write disble instruction to the chip.
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*/
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static inline int write_disable(struct spi_nor *nor)
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{
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return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
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}
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static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
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{
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return mtd->priv;
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}
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/* Enable/disable 4-byte addressing mode. */
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static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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int enable)
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{
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int status;
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bool need_wren = false;
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u8 cmd;
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switch (JEDEC_MFR(info)) {
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case SNOR_MFR_MICRON:
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/* Some Micron need WREN command; all will accept it */
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need_wren = true;
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case SNOR_MFR_MACRONIX:
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case SNOR_MFR_WINBOND:
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if (need_wren)
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write_enable(nor);
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cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
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status = nor->write_reg(nor, cmd, NULL, 0);
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if (need_wren)
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write_disable(nor);
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return status;
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default:
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/* Spansion style */
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nor->cmd_buf[0] = enable << 7;
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return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
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}
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}
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static inline int spi_nor_sr_ready(struct spi_nor *nor)
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{
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int sr = read_sr(nor);
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if (sr < 0)
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return sr;
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else
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return !(sr & SR_WIP);
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}
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static inline int spi_nor_fsr_ready(struct spi_nor *nor)
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{
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int fsr = read_fsr(nor);
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if (fsr < 0)
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return fsr;
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else
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return fsr & FSR_READY;
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}
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static int spi_nor_ready(struct spi_nor *nor)
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{
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int sr, fsr;
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sr = spi_nor_sr_ready(nor);
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if (sr < 0)
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return sr;
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fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
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if (fsr < 0)
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return fsr;
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return sr && fsr;
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}
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/*
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* Service routine to read status register until ready, or timeout occurs.
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* Returns non-zero if error.
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*/
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static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
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unsigned long timeout_jiffies)
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{
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unsigned long deadline;
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int timeout = 0, ret;
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deadline = jiffies + timeout_jiffies;
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while (!timeout) {
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if (time_after_eq(jiffies, deadline))
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timeout = 1;
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ret = spi_nor_ready(nor);
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if (ret < 0)
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return ret;
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if (ret)
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return 0;
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cond_resched();
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}
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dev_err(nor->dev, "flash operation timed out\n");
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return -ETIMEDOUT;
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}
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static int spi_nor_wait_till_ready(struct spi_nor *nor)
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{
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return spi_nor_wait_till_ready_with_timeout(nor,
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DEFAULT_READY_WAIT_JIFFIES);
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}
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/*
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* Erase the whole flash memory
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*
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* Returns 0 if successful, non-zero otherwise.
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*/
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static int erase_chip(struct spi_nor *nor)
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{
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dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
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return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
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}
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static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
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{
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int ret = 0;
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mutex_lock(&nor->lock);
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if (nor->prepare) {
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ret = nor->prepare(nor, ops);
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if (ret) {
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dev_err(nor->dev, "failed in the preparation.\n");
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mutex_unlock(&nor->lock);
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return ret;
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}
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}
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return ret;
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}
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static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
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{
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if (nor->unprepare)
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nor->unprepare(nor, ops);
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mutex_unlock(&nor->lock);
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}
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/*
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* Initiate the erasure of a single sector
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*/
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static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
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{
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u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
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int i;
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if (nor->erase)
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return nor->erase(nor, addr);
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/*
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* Default implementation, if driver doesn't have a specialized HW
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* control
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*/
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for (i = nor->addr_width - 1; i >= 0; i--) {
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buf[i] = addr & 0xff;
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addr >>= 8;
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}
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return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
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}
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/*
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* Erase an address range on the nor chip. The address range may extend
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* one or more erase sectors. Return an error is there is a problem erasing.
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*/
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static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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{
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struct spi_nor *nor = mtd_to_spi_nor(mtd);
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u32 addr, len;
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uint32_t rem;
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int ret;
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dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
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(long long)instr->len);
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div_u64_rem(instr->len, mtd->erasesize, &rem);
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if (rem)
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return -EINVAL;
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addr = instr->addr;
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len = instr->len;
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ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
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if (ret)
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return ret;
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/* whole-chip erase? */
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if (len == mtd->size) {
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unsigned long timeout;
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write_enable(nor);
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if (erase_chip(nor)) {
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ret = -EIO;
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goto erase_err;
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}
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/*
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* Scale the timeout linearly with the size of the flash, with
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* a minimum calibrated to an old 2MB flash. We could try to
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* pull these from CFI/SFDP, but these values should be good
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* enough for now.
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*/
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timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
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CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
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(unsigned long)(mtd->size / SZ_2M));
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ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
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if (ret)
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goto erase_err;
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/* REVISIT in some cases we could speed up erasing large regions
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* by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
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* to use "small sector erase", but that's not always optimal.
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*/
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/* "sector"-at-a-time erase */
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} else {
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while (len) {
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write_enable(nor);
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ret = spi_nor_erase_sector(nor, addr);
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if (ret)
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goto erase_err;
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addr += mtd->erasesize;
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len -= mtd->erasesize;
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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goto erase_err;
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}
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}
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write_disable(nor);
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erase_err:
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spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
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instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
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mtd_erase_callback(instr);
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return ret;
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}
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static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
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uint64_t *len)
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{
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struct mtd_info *mtd = &nor->mtd;
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u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
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int shift = ffs(mask) - 1;
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int pow;
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if (!(sr & mask)) {
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/* No protection */
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*ofs = 0;
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*len = 0;
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} else {
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pow = ((sr & mask) ^ mask) >> shift;
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*len = mtd->size >> pow;
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*ofs = mtd->size - *len;
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}
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}
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/*
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* Return 1 if the entire region is locked, 0 otherwise
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*/
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static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
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u8 sr)
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{
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loff_t lock_offs;
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uint64_t lock_len;
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stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
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return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
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}
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/*
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* Lock a region of the flash. Compatible with ST Micro and similar flash.
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* Supports only the block protection bits BP{0,1,2} in the status register
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* (SR). Does not support these features found in newer SR bitfields:
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* - TB: top/bottom protect - only handle TB=0 (top protect)
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* - SEC: sector/block protect - only handle SEC=0 (block protect)
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* - CMP: complement protect - only support CMP=0 (range is not complemented)
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*
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* Sample table portion for 8MB flash (Winbond w25q64fw):
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*
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* SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
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* --------------------------------------------------------------------------
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* X | X | 0 | 0 | 0 | NONE | NONE
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* 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
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* 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
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* 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
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* 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
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* 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
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* 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
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* X | X | 1 | 1 | 1 | 8 MB | ALL
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*
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* Returns negative on errors, 0 on success.
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*/
|
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static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
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{
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struct mtd_info *mtd = &nor->mtd;
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int status_old, status_new;
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u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
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u8 shift = ffs(mask) - 1, pow, val;
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int ret;
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|
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status_old = read_sr(nor);
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if (status_old < 0)
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return status_old;
|
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|
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/* SPI NOR always locks to the end */
|
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if (ofs + len != mtd->size) {
|
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/* Does combined region extend to end? */
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if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len,
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status_old))
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return -EINVAL;
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len = mtd->size - ofs;
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}
|
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|
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/*
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* Need smallest pow such that:
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*
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* 1 / (2^pow) <= (len / size)
|
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*
|
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* so (assuming power-of-2 size) we do:
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*
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* pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
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*/
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pow = ilog2(mtd->size) - ilog2(len);
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val = mask - (pow << shift);
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if (val & ~mask)
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return -EINVAL;
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/* Don't "lock" with no region! */
|
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if (!(val & mask))
|
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return -EINVAL;
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|
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status_new = (status_old & ~mask) | val;
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|
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/* Only modify protection if it will not unlock other areas */
|
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if ((status_new & mask) <= (status_old & mask))
|
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return -EINVAL;
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|
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write_enable(nor);
|
|
ret = write_sr(nor, status_new);
|
|
if (ret)
|
|
return ret;
|
|
return spi_nor_wait_till_ready(nor);
|
|
}
|
|
|
|
/*
|
|
* Unlock a region of the flash. See stm_lock() for more info
|
|
*
|
|
* Returns negative on errors, 0 on success.
|
|
*/
|
|
static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
|
|
{
|
|
struct mtd_info *mtd = &nor->mtd;
|
|
int status_old, status_new;
|
|
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
|
|
u8 shift = ffs(mask) - 1, pow, val;
|
|
int ret;
|
|
|
|
status_old = read_sr(nor);
|
|
if (status_old < 0)
|
|
return status_old;
|
|
|
|
/* Cannot unlock; would unlock larger region than requested */
|
|
if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize,
|
|
status_old))
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Need largest pow such that:
|
|
*
|
|
* 1 / (2^pow) >= (len / size)
|
|
*
|
|
* so (assuming power-of-2 size) we do:
|
|
*
|
|
* pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
|
|
*/
|
|
pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len));
|
|
if (ofs + len == mtd->size) {
|
|
val = 0; /* fully unlocked */
|
|
} else {
|
|
val = mask - (pow << shift);
|
|
/* Some power-of-two sizes are not supported */
|
|
if (val & ~mask)
|
|
return -EINVAL;
|
|
}
|
|
|
|
status_new = (status_old & ~mask) | val;
|
|
|
|
/* Only modify protection if it will not lock other areas */
|
|
if ((status_new & mask) >= (status_old & mask))
|
|
return -EINVAL;
|
|
|
|
write_enable(nor);
|
|
ret = write_sr(nor, status_new);
|
|
if (ret)
|
|
return ret;
|
|
return spi_nor_wait_till_ready(nor);
|
|
}
|
|
|
|
/*
|
|
* Check if a region of the flash is (completely) locked. See stm_lock() for
|
|
* more info.
|
|
*
|
|
* Returns 1 if entire region is locked, 0 if any portion is unlocked, and
|
|
* negative on errors.
|
|
*/
|
|
static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
|
|
{
|
|
int status;
|
|
|
|
status = read_sr(nor);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
return stm_is_locked_sr(nor, ofs, len, status);
|
|
}
|
|
|
|
static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
int ret;
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nor->flash_lock(nor, ofs, len);
|
|
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
|
|
return ret;
|
|
}
|
|
|
|
static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
int ret;
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nor->flash_unlock(nor, ofs, len);
|
|
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
|
|
return ret;
|
|
}
|
|
|
|
static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
int ret;
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nor->flash_is_locked(nor, ofs, len);
|
|
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
|
|
return ret;
|
|
}
|
|
|
|
/* Used when the "_ext_id" is two bytes at most */
|
|
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
|
|
.id = { \
|
|
((_jedec_id) >> 16) & 0xff, \
|
|
((_jedec_id) >> 8) & 0xff, \
|
|
(_jedec_id) & 0xff, \
|
|
((_ext_id) >> 8) & 0xff, \
|
|
(_ext_id) & 0xff, \
|
|
}, \
|
|
.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
|
|
.sector_size = (_sector_size), \
|
|
.n_sectors = (_n_sectors), \
|
|
.page_size = 256, \
|
|
.flags = (_flags),
|
|
|
|
#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
|
|
.id = { \
|
|
((_jedec_id) >> 16) & 0xff, \
|
|
((_jedec_id) >> 8) & 0xff, \
|
|
(_jedec_id) & 0xff, \
|
|
((_ext_id) >> 16) & 0xff, \
|
|
((_ext_id) >> 8) & 0xff, \
|
|
(_ext_id) & 0xff, \
|
|
}, \
|
|
.id_len = 6, \
|
|
.sector_size = (_sector_size), \
|
|
.n_sectors = (_n_sectors), \
|
|
.page_size = 256, \
|
|
.flags = (_flags),
|
|
|
|
#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
|
|
.sector_size = (_sector_size), \
|
|
.n_sectors = (_n_sectors), \
|
|
.page_size = (_page_size), \
|
|
.addr_width = (_addr_width), \
|
|
.flags = (_flags),
|
|
|
|
/* NOTE: double check command sets and memory organization when you add
|
|
* more nor chips. This current list focusses on newer chips, which
|
|
* have been converging on command sets which including JEDEC ID.
|
|
*
|
|
* All newly added entries should describe *hardware* and should use SECT_4K
|
|
* (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
|
|
* scenarios excluding small sectors there is config option that can be
|
|
* disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
|
|
* For historical (and compatibility) reasons (before we got above config) some
|
|
* old entries may be missing 4K flag.
|
|
*/
|
|
static const struct flash_info spi_nor_ids[] = {
|
|
/* Atmel -- some are (confusingly) marketed as "DataFlash" */
|
|
{ "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
|
|
{ "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
|
|
|
|
{ "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
|
|
|
|
{ "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
|
|
{ "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
|
|
{ "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
|
|
|
|
{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
|
|
|
|
/* EON -- en25xxx */
|
|
{ "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
|
|
{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
|
|
{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
|
|
{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
|
|
{ "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
|
|
{ "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
|
|
|
|
/* ESMT */
|
|
{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
|
|
|
|
/* Everspin */
|
|
{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
|
|
/* Fujitsu */
|
|
{ "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
|
|
|
|
/* GigaDevice */
|
|
{ "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
|
|
|
|
/* Intel/Numonyx -- xxxs33b */
|
|
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
|
|
{ "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
|
|
{ "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
|
|
|
|
/* ISSI */
|
|
{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
|
|
|
|
/* Macronix */
|
|
{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
|
|
{ "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
|
|
{ "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
|
|
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
|
|
{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
|
|
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
|
|
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
|
|
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
|
|
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
|
|
|
|
/* Micron */
|
|
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
|
|
{ "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
|
|
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
|
|
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
|
|
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
|
|
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
|
|
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
|
|
|
|
/* PMC */
|
|
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
|
|
{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
|
|
{ "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
|
|
|
|
/* Spansion -- single (large) sector size only, at least
|
|
* for the chips listed here (without boot sectors).
|
|
*/
|
|
{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
|
|
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
|
|
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
|
|
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
|
|
{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
|
|
{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
|
|
{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
|
|
{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
|
|
{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
|
|
{ "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
|
|
|
|
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
|
|
{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
|
|
{ "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
|
|
{ "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
|
|
{ "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
|
|
{ "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
|
|
{ "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
|
|
{ "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
|
|
{ "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
|
|
{ "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
|
|
|
|
/* ST Microelectronics -- newer production may have feature updates */
|
|
{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
|
|
{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
|
|
{ "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
|
|
{ "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
|
|
{ "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
|
|
{ "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
|
|
{ "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
|
|
{ "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
|
|
{ "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
|
|
|
|
{ "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
|
|
{ "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
|
|
{ "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
|
|
{ "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
|
|
{ "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
|
|
{ "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
|
|
{ "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
|
|
{ "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
|
|
{ "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
|
|
|
|
{ "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
|
|
{ "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
|
|
{ "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
|
|
|
|
{ "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
|
|
{ "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
|
|
{ "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
|
|
|
|
{ "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
|
|
{ "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
|
|
{ "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
|
|
|
|
/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
|
|
{ "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
|
|
{ "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
|
|
{ "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
|
|
{ "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
|
|
{ "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
|
|
{ "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
|
|
{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
|
|
{ "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
|
|
{ "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
|
{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
|
|
{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
|
|
{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
|
|
{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
|
|
|
|
/* Catalyst / On Semiconductor -- non-JEDEC */
|
|
{ "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
{ },
|
|
};
|
|
|
|
static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
|
|
{
|
|
int tmp;
|
|
u8 id[SPI_NOR_MAX_ID_LEN];
|
|
const struct flash_info *info;
|
|
|
|
tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
|
|
if (tmp < 0) {
|
|
dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
|
|
return ERR_PTR(tmp);
|
|
}
|
|
|
|
for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
|
|
info = &spi_nor_ids[tmp];
|
|
if (info->id_len) {
|
|
if (!memcmp(info->id, id, info->id_len))
|
|
return &spi_nor_ids[tmp];
|
|
}
|
|
}
|
|
dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
|
|
id[0], id[1], id[2]);
|
|
return ERR_PTR(-ENODEV);
|
|
}
|
|
|
|
static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
|
|
size_t *retlen, u_char *buf)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
int ret;
|
|
|
|
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nor->read(nor, from, len, retlen, buf);
|
|
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
|
|
return ret;
|
|
}
|
|
|
|
static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
|
|
size_t *retlen, const u_char *buf)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
size_t actual;
|
|
int ret;
|
|
|
|
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
write_enable(nor);
|
|
|
|
nor->sst_write_second = false;
|
|
|
|
actual = to % 2;
|
|
/* Start write from odd address. */
|
|
if (actual) {
|
|
nor->program_opcode = SPINOR_OP_BP;
|
|
|
|
/* write one byte. */
|
|
nor->write(nor, to, 1, retlen, buf);
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto time_out;
|
|
}
|
|
to += actual;
|
|
|
|
/* Write out most of the data here. */
|
|
for (; actual < len - 1; actual += 2) {
|
|
nor->program_opcode = SPINOR_OP_AAI_WP;
|
|
|
|
/* write two bytes. */
|
|
nor->write(nor, to, 2, retlen, buf + actual);
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto time_out;
|
|
to += 2;
|
|
nor->sst_write_second = true;
|
|
}
|
|
nor->sst_write_second = false;
|
|
|
|
write_disable(nor);
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto time_out;
|
|
|
|
/* Write out trailing byte if it exists. */
|
|
if (actual != len) {
|
|
write_enable(nor);
|
|
|
|
nor->program_opcode = SPINOR_OP_BP;
|
|
nor->write(nor, to, 1, retlen, buf + actual);
|
|
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto time_out;
|
|
write_disable(nor);
|
|
}
|
|
time_out:
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Write an address range to the nor chip. Data must be written in
|
|
* FLASH_PAGESIZE chunks. The address range may be any size provided
|
|
* it is within the physical boundaries.
|
|
*/
|
|
static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
|
|
size_t *retlen, const u_char *buf)
|
|
{
|
|
struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
u32 page_offset, page_size, i;
|
|
int ret;
|
|
|
|
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
|
|
|
|
ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
write_enable(nor);
|
|
|
|
page_offset = to & (nor->page_size - 1);
|
|
|
|
/* do all the bytes fit onto one page? */
|
|
if (page_offset + len <= nor->page_size) {
|
|
nor->write(nor, to, len, retlen, buf);
|
|
} else {
|
|
/* the size of data remaining on the first page */
|
|
page_size = nor->page_size - page_offset;
|
|
nor->write(nor, to, page_size, retlen, buf);
|
|
|
|
/* write everything in nor->page_size chunks */
|
|
for (i = page_size; i < len; i += page_size) {
|
|
page_size = len - i;
|
|
if (page_size > nor->page_size)
|
|
page_size = nor->page_size;
|
|
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
goto write_err;
|
|
|
|
write_enable(nor);
|
|
|
|
nor->write(nor, to + i, page_size, retlen, buf + i);
|
|
}
|
|
}
|
|
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
write_err:
|
|
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
|
|
return ret;
|
|
}
|
|
|
|
static int macronix_quad_enable(struct spi_nor *nor)
|
|
{
|
|
int ret, val;
|
|
|
|
val = read_sr(nor);
|
|
if (val < 0)
|
|
return val;
|
|
write_enable(nor);
|
|
|
|
write_sr(nor, val | SR_QUAD_EN_MX);
|
|
|
|
if (spi_nor_wait_till_ready(nor))
|
|
return 1;
|
|
|
|
ret = read_sr(nor);
|
|
if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
|
|
dev_err(nor->dev, "Macronix Quad bit not set\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write status Register and configuration register with 2 bytes
|
|
* The first byte will be written to the status register, while the
|
|
* second byte will be written to the configuration register.
|
|
* Return negative if error occured.
|
|
*/
|
|
static int write_sr_cr(struct spi_nor *nor, u16 val)
|
|
{
|
|
nor->cmd_buf[0] = val & 0xff;
|
|
nor->cmd_buf[1] = (val >> 8);
|
|
|
|
return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
|
|
}
|
|
|
|
static int spansion_quad_enable(struct spi_nor *nor)
|
|
{
|
|
int ret;
|
|
int quad_en = CR_QUAD_EN_SPAN << 8;
|
|
|
|
write_enable(nor);
|
|
|
|
ret = write_sr_cr(nor, quad_en);
|
|
if (ret < 0) {
|
|
dev_err(nor->dev,
|
|
"error while writing configuration register\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* read back and check it */
|
|
ret = read_cr(nor);
|
|
if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
|
|
dev_err(nor->dev, "Spansion Quad bit not set\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int micron_quad_enable(struct spi_nor *nor)
|
|
{
|
|
int ret;
|
|
u8 val;
|
|
|
|
ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
|
|
if (ret < 0) {
|
|
dev_err(nor->dev, "error %d reading EVCR\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
write_enable(nor);
|
|
|
|
/* set EVCR, enable quad I/O */
|
|
nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
|
|
ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
|
|
if (ret < 0) {
|
|
dev_err(nor->dev, "error while writing EVCR register\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = spi_nor_wait_till_ready(nor);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* read EVCR and check it */
|
|
ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
|
|
if (ret < 0) {
|
|
dev_err(nor->dev, "error %d reading EVCR\n", ret);
|
|
return ret;
|
|
}
|
|
if (val & EVCR_QUAD_EN_MICRON) {
|
|
dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
|
|
{
|
|
int status;
|
|
|
|
switch (JEDEC_MFR(info)) {
|
|
case SNOR_MFR_MACRONIX:
|
|
status = macronix_quad_enable(nor);
|
|
if (status) {
|
|
dev_err(nor->dev, "Macronix quad-read not enabled\n");
|
|
return -EINVAL;
|
|
}
|
|
return status;
|
|
case SNOR_MFR_MICRON:
|
|
status = micron_quad_enable(nor);
|
|
if (status) {
|
|
dev_err(nor->dev, "Micron quad-read not enabled\n");
|
|
return -EINVAL;
|
|
}
|
|
return status;
|
|
default:
|
|
status = spansion_quad_enable(nor);
|
|
if (status) {
|
|
dev_err(nor->dev, "Spansion quad-read not enabled\n");
|
|
return -EINVAL;
|
|
}
|
|
return status;
|
|
}
|
|
}
|
|
|
|
static int spi_nor_check(struct spi_nor *nor)
|
|
{
|
|
if (!nor->dev || !nor->read || !nor->write ||
|
|
!nor->read_reg || !nor->write_reg) {
|
|
pr_err("spi-nor: please fill all the necessary fields!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
|
|
{
|
|
const struct flash_info *info = NULL;
|
|
struct device *dev = nor->dev;
|
|
struct mtd_info *mtd = &nor->mtd;
|
|
struct device_node *np = spi_nor_get_flash_node(nor);
|
|
int ret;
|
|
int i;
|
|
|
|
ret = spi_nor_check(nor);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (name)
|
|
info = spi_nor_match_id(name);
|
|
/* Try to auto-detect if chip name wasn't specified or not found */
|
|
if (!info)
|
|
info = spi_nor_read_id(nor);
|
|
if (IS_ERR_OR_NULL(info))
|
|
return -ENOENT;
|
|
|
|
/*
|
|
* If caller has specified name of flash model that can normally be
|
|
* detected using JEDEC, let's verify it.
|
|
*/
|
|
if (name && info->id_len) {
|
|
const struct flash_info *jinfo;
|
|
|
|
jinfo = spi_nor_read_id(nor);
|
|
if (IS_ERR(jinfo)) {
|
|
return PTR_ERR(jinfo);
|
|
} else if (jinfo != info) {
|
|
/*
|
|
* JEDEC knows better, so overwrite platform ID. We
|
|
* can't trust partitions any longer, but we'll let
|
|
* mtd apply them anyway, since some partitions may be
|
|
* marked read-only, and we don't want to lose that
|
|
* information, even if it's not 100% accurate.
|
|
*/
|
|
dev_warn(dev, "found %s, expected %s\n",
|
|
jinfo->name, info->name);
|
|
info = jinfo;
|
|
}
|
|
}
|
|
|
|
mutex_init(&nor->lock);
|
|
|
|
/*
|
|
* Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
|
|
* with the software protection bits set
|
|
*/
|
|
|
|
if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
|
|
JEDEC_MFR(info) == SNOR_MFR_INTEL ||
|
|
JEDEC_MFR(info) == SNOR_MFR_SST) {
|
|
write_enable(nor);
|
|
write_sr(nor, 0);
|
|
}
|
|
|
|
if (!mtd->name)
|
|
mtd->name = dev_name(dev);
|
|
mtd->priv = nor;
|
|
mtd->type = MTD_NORFLASH;
|
|
mtd->writesize = 1;
|
|
mtd->flags = MTD_CAP_NORFLASH;
|
|
mtd->size = info->sector_size * info->n_sectors;
|
|
mtd->_erase = spi_nor_erase;
|
|
mtd->_read = spi_nor_read;
|
|
|
|
/* NOR protection support for STmicro/Micron chips and similar */
|
|
if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
|
|
nor->flash_lock = stm_lock;
|
|
nor->flash_unlock = stm_unlock;
|
|
nor->flash_is_locked = stm_is_locked;
|
|
}
|
|
|
|
if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
|
|
mtd->_lock = spi_nor_lock;
|
|
mtd->_unlock = spi_nor_unlock;
|
|
mtd->_is_locked = spi_nor_is_locked;
|
|
}
|
|
|
|
/* sst nor chips use AAI word program */
|
|
if (info->flags & SST_WRITE)
|
|
mtd->_write = sst_write;
|
|
else
|
|
mtd->_write = spi_nor_write;
|
|
|
|
if (info->flags & USE_FSR)
|
|
nor->flags |= SNOR_F_USE_FSR;
|
|
|
|
#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
|
|
/* prefer "small sector" erase if possible */
|
|
if (info->flags & SECT_4K) {
|
|
nor->erase_opcode = SPINOR_OP_BE_4K;
|
|
mtd->erasesize = 4096;
|
|
} else if (info->flags & SECT_4K_PMC) {
|
|
nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
|
|
mtd->erasesize = 4096;
|
|
} else
|
|
#endif
|
|
{
|
|
nor->erase_opcode = SPINOR_OP_SE;
|
|
mtd->erasesize = info->sector_size;
|
|
}
|
|
|
|
if (info->flags & SPI_NOR_NO_ERASE)
|
|
mtd->flags |= MTD_NO_ERASE;
|
|
|
|
mtd->dev.parent = dev;
|
|
nor->page_size = info->page_size;
|
|
mtd->writebufsize = nor->page_size;
|
|
|
|
if (np) {
|
|
/* If we were instantiated by DT, use it */
|
|
if (of_property_read_bool(np, "m25p,fast-read"))
|
|
nor->flash_read = SPI_NOR_FAST;
|
|
else
|
|
nor->flash_read = SPI_NOR_NORMAL;
|
|
} else {
|
|
/* If we weren't instantiated by DT, default to fast-read */
|
|
nor->flash_read = SPI_NOR_FAST;
|
|
}
|
|
|
|
/* Some devices cannot do fast-read, no matter what DT tells us */
|
|
if (info->flags & SPI_NOR_NO_FR)
|
|
nor->flash_read = SPI_NOR_NORMAL;
|
|
|
|
/* Quad/Dual-read mode takes precedence over fast/normal */
|
|
if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
|
|
ret = set_quad_mode(nor, info);
|
|
if (ret) {
|
|
dev_err(dev, "quad mode not supported\n");
|
|
return ret;
|
|
}
|
|
nor->flash_read = SPI_NOR_QUAD;
|
|
} else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
|
|
nor->flash_read = SPI_NOR_DUAL;
|
|
}
|
|
|
|
/* Default commands */
|
|
switch (nor->flash_read) {
|
|
case SPI_NOR_QUAD:
|
|
nor->read_opcode = SPINOR_OP_READ_1_1_4;
|
|
break;
|
|
case SPI_NOR_DUAL:
|
|
nor->read_opcode = SPINOR_OP_READ_1_1_2;
|
|
break;
|
|
case SPI_NOR_FAST:
|
|
nor->read_opcode = SPINOR_OP_READ_FAST;
|
|
break;
|
|
case SPI_NOR_NORMAL:
|
|
nor->read_opcode = SPINOR_OP_READ;
|
|
break;
|
|
default:
|
|
dev_err(dev, "No Read opcode defined\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
nor->program_opcode = SPINOR_OP_PP;
|
|
|
|
if (info->addr_width)
|
|
nor->addr_width = info->addr_width;
|
|
else if (mtd->size > 0x1000000) {
|
|
/* enable 4-byte addressing if the device exceeds 16MiB */
|
|
nor->addr_width = 4;
|
|
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
|
|
/* Dedicated 4-byte command set */
|
|
switch (nor->flash_read) {
|
|
case SPI_NOR_QUAD:
|
|
nor->read_opcode = SPINOR_OP_READ4_1_1_4;
|
|
break;
|
|
case SPI_NOR_DUAL:
|
|
nor->read_opcode = SPINOR_OP_READ4_1_1_2;
|
|
break;
|
|
case SPI_NOR_FAST:
|
|
nor->read_opcode = SPINOR_OP_READ4_FAST;
|
|
break;
|
|
case SPI_NOR_NORMAL:
|
|
nor->read_opcode = SPINOR_OP_READ4;
|
|
break;
|
|
}
|
|
nor->program_opcode = SPINOR_OP_PP_4B;
|
|
/* No small sector erase for 4-byte command set */
|
|
nor->erase_opcode = SPINOR_OP_SE_4B;
|
|
mtd->erasesize = info->sector_size;
|
|
} else
|
|
set_4byte(nor, info, 1);
|
|
} else {
|
|
nor->addr_width = 3;
|
|
}
|
|
|
|
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
|
|
dev_err(dev, "address width is too large: %u\n",
|
|
nor->addr_width);
|
|
return -EINVAL;
|
|
}
|
|
|
|
nor->read_dummy = spi_nor_read_dummy_cycles(nor);
|
|
|
|
dev_info(dev, "%s (%lld Kbytes)\n", info->name,
|
|
(long long)mtd->size >> 10);
|
|
|
|
dev_dbg(dev,
|
|
"mtd .name = %s, .size = 0x%llx (%lldMiB), "
|
|
".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
|
|
mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
|
|
mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
|
|
|
|
if (mtd->numeraseregions)
|
|
for (i = 0; i < mtd->numeraseregions; i++)
|
|
dev_dbg(dev,
|
|
"mtd.eraseregions[%d] = { .offset = 0x%llx, "
|
|
".erasesize = 0x%.8x (%uKiB), "
|
|
".numblocks = %d }\n",
|
|
i, (long long)mtd->eraseregions[i].offset,
|
|
mtd->eraseregions[i].erasesize,
|
|
mtd->eraseregions[i].erasesize / 1024,
|
|
mtd->eraseregions[i].numblocks);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_nor_scan);
|
|
|
|
static const struct flash_info *spi_nor_match_id(const char *name)
|
|
{
|
|
const struct flash_info *id = spi_nor_ids;
|
|
|
|
while (id->name) {
|
|
if (!strcmp(name, id->name))
|
|
return id;
|
|
id++;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
|
|
MODULE_AUTHOR("Mike Lavender");
|
|
MODULE_DESCRIPTION("framework for SPI NOR");
|