55486091bd
Our core PLLs are intended to be configured once and left alone. With the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would change PLLD just to get closer to the requested DSI clock, thus changing PLLD_PER, the UART and ethernet PHY clock rates downstream of it, and breaking ethernet. We *do* want PLLH to change so that PLLH_AUX can be exactly the value we want, though. Thus, we need to have a per-divider policy of whether to pass rate changes up. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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| .. | ||
| clk-bcm63xx.c | ||
| clk-bcm281xx.c | ||
| clk-bcm2835-aux.c | ||
| clk-bcm2835.c | ||
| clk-bcm21664.c | ||
| clk-bcm53573-ilp.c | ||
| clk-cygnus.c | ||
| clk-iproc-armpll.c | ||
| clk-iproc-asiu.c | ||
| clk-iproc-pll.c | ||
| clk-iproc.h | ||
| clk-kona-setup.c | ||
| clk-kona.c | ||
| clk-kona.h | ||
| clk-ns2.c | ||
| clk-nsp.c | ||
| Kconfig | ||
| Makefile | ||