![Matt Roper](/assets/img/avatar_default.png)
In addition to calculating final watermarks, let's also pre-calculate a set of intermediate watermark values at atomic check time. These intermediate watermarks are a combination of the watermarks for the old state and the new state; they should satisfy the requirements of both states which means they can be programmed immediately when we commit the atomic state (without waiting for a vblank). Once the vblank does happen, we can then re-program watermarks to the more optimal final value. v2: Significant rebasing/rewriting. v3: - Move 'need_postvbl_update' flag to CRTC state (Daniel) - Don't forget to check intermediate watermark values for validity (Maarten) - Don't due async watermark optimization; just do it at the end of the atomic transaction, after waiting for vblanks. We do want it to be async eventually, but adding that now will cause more trouble for Maarten's in-progress work. (Maarten) - Don't allocate space in crtc_state for intermediate watermarks on platforms that don't need it (gen9+). - Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit now that ilk_update_wm is gone. v4: - Add a wm_mutex to cover updates to intel_crtc->active and the need_postvbl_update flag. Since we don't have async yet it isn't terribly important yet, but might as well add it now. - Change interface to program watermarks. Platforms will now expose .initial_watermarks() and .optimize_watermarks() functions to do watermark programming. These should lock wm_mutex, copy the appropriate state values into intel_crtc->active, and then call the internal program watermarks function. v5: - Skip intermediate watermark calculation/check during initial hardware readout since we don't trust the existing HW values (and don't have valid values of our own yet). - Don't try to call .optimize_watermarks() on platforms that don't have atomic watermarks yet. (Maarten) v6: - Rebase v7: - Further rebase v8: - A few minor indentation and line length fixes v9: - Yet another rebase since Maarten's patches reworked a bunch of the code (wm_pre, wm_post, etc.) that this was previously based on. v10: - Move wm_mutex to dev_priv to protect against racing commits against disjoint CRTC sets. (Maarten) - Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten) Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1452108870-24204-1-git-send-email-matthew.d.roper@intel.com Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
314 lines
9.2 KiB
C
314 lines
9.2 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* DOC: atomic modeset support
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*
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* The functions here implement the state management and hardware programming
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* dispatch required by the atomic modeset infrastructure.
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* See intel_atomic_plane.c for the plane-specific atomic functionality.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "intel_drv.h"
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/**
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* intel_connector_atomic_get_property - fetch connector property value
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* @connector: connector to fetch property for
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* @state: state containing the property value
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* @property: property to look up
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* @val: pointer to write property value into
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*
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* The DRM core does not store shadow copies of properties for
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* atomic-capable drivers. This entrypoint is used to fetch
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* the current value of a driver-specific connector property.
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*/
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int
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intel_connector_atomic_get_property(struct drm_connector *connector,
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const struct drm_connector_state *state,
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struct drm_property *property,
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uint64_t *val)
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{
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int i;
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/*
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* TODO: We only have atomic modeset for planes at the moment, so the
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* crtc/connector code isn't quite ready yet. Until it's ready,
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* continue to look up all property values in the DRM's shadow copy
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* in obj->properties->values[].
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*
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* When the crtc/connector state work matures, this function should
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* be updated to read the values out of the state structure instead.
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*/
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for (i = 0; i < connector->base.properties->count; i++) {
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if (connector->base.properties->properties[i] == property) {
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*val = connector->base.properties->values[i];
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return 0;
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}
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}
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return -EINVAL;
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}
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/*
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* intel_crtc_duplicate_state - duplicate crtc state
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* @crtc: drm crtc
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*
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* Allocates and returns a copy of the crtc state (both common and
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* Intel-specific) for the specified crtc.
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*
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* Returns: The newly allocated crtc state, or NULL on failure.
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*/
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struct drm_crtc_state *
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intel_crtc_duplicate_state(struct drm_crtc *crtc)
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{
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struct intel_crtc_state *crtc_state;
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crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
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if (!crtc_state)
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return NULL;
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__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
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crtc_state->update_pipe = false;
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crtc_state->disable_lp_wm = false;
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crtc_state->disable_cxsr = false;
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crtc_state->wm_changed = false;
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crtc_state->wm.need_postvbl_update = false;
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return &crtc_state->base;
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}
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/**
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* intel_crtc_destroy_state - destroy crtc state
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* @crtc: drm crtc
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*
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* Destroys the crtc state (both common and Intel-specific) for the
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* specified crtc.
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*/
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void
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intel_crtc_destroy_state(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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drm_atomic_helper_crtc_destroy_state(crtc, state);
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}
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/**
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* intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
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* @dev: DRM device
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* @crtc: intel crtc
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* @crtc_state: incoming crtc_state to validate and setup scalers
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*
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* This function sets up scalers based on staged scaling requests for
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* a @crtc and its planes. It is called from crtc level check path. If request
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* is a supportable request, it attaches scalers to requested planes and crtc.
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*
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* This function takes into account the current scaler(s) in use by any planes
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* not being part of this atomic state
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*
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* Returns:
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* 0 - scalers were setup succesfully
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* error code - otherwise
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*/
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int intel_atomic_setup_scalers(struct drm_device *dev,
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struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_plane *plane = NULL;
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struct intel_plane *intel_plane;
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struct intel_plane_state *plane_state = NULL;
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struct intel_crtc_scaler_state *scaler_state =
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&crtc_state->scaler_state;
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struct drm_atomic_state *drm_state = crtc_state->base.state;
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int num_scalers_need;
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int i, j;
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num_scalers_need = hweight32(scaler_state->scaler_users);
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/*
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* High level flow:
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* - staged scaler requests are already in scaler_state->scaler_users
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* - check whether staged scaling requests can be supported
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* - add planes using scalers that aren't in current transaction
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* - assign scalers to requested users
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* - as part of plane commit, scalers will be committed
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* (i.e., either attached or detached) to respective planes in hw
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* - as part of crtc_commit, scaler will be either attached or detached
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* to crtc in hw
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*/
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/* fail if required scalers > available scalers */
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if (num_scalers_need > intel_crtc->num_scalers){
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DRM_DEBUG_KMS("Too many scaling requests %d > %d\n",
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num_scalers_need, intel_crtc->num_scalers);
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return -EINVAL;
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}
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/* walkthrough scaler_users bits and start assigning scalers */
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for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
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int *scaler_id;
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const char *name;
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int idx;
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/* skip if scaler not required */
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if (!(scaler_state->scaler_users & (1 << i)))
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continue;
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if (i == SKL_CRTC_INDEX) {
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name = "CRTC";
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idx = intel_crtc->base.base.id;
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/* panel fitter case: assign as a crtc scaler */
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scaler_id = &scaler_state->scaler_id;
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} else {
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name = "PLANE";
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/* plane scaler case: assign as a plane scaler */
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/* find the plane that set the bit as scaler_user */
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plane = drm_state->planes[i];
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/*
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* to enable/disable hq mode, add planes that are using scaler
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* into this transaction
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*/
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if (!plane) {
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struct drm_plane_state *state;
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plane = drm_plane_from_index(dev, i);
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state = drm_atomic_get_plane_state(drm_state, plane);
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if (IS_ERR(state)) {
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DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
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plane->base.id);
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return PTR_ERR(state);
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}
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/*
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* the plane is added after plane checks are run,
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* but since this plane is unchanged just do the
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* minimum required validation.
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*/
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crtc_state->base.planes_changed = true;
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}
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intel_plane = to_intel_plane(plane);
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idx = plane->base.id;
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/* plane on different crtc cannot be a scaler user of this crtc */
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if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) {
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continue;
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}
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plane_state = to_intel_plane_state(drm_state->plane_states[i]);
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scaler_id = &plane_state->scaler_id;
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}
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if (*scaler_id < 0) {
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/* find a free scaler */
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for (j = 0; j < intel_crtc->num_scalers; j++) {
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if (!scaler_state->scalers[j].in_use) {
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scaler_state->scalers[j].in_use = 1;
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*scaler_id = j;
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DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
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intel_crtc->pipe, *scaler_id, name, idx);
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break;
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}
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}
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}
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if (WARN_ON(*scaler_id < 0)) {
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DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n", name, idx);
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continue;
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}
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/* set scaler mode */
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if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
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/*
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* when only 1 scaler is in use on either pipe A or B,
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* scaler 0 operates in high quality (HQ) mode.
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* In this case use scaler 0 to take advantage of HQ mode
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*/
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*scaler_id = 0;
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scaler_state->scalers[0].in_use = 1;
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scaler_state->scalers[0].mode = PS_SCALER_MODE_HQ;
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scaler_state->scalers[1].in_use = 0;
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} else {
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scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_DYN;
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}
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}
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return 0;
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}
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static void
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intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll_config *shared_dpll)
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{
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enum intel_dpll_id i;
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/* Copy shared dpll state */
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for (i = 0; i < dev_priv->num_shared_dpll; i++) {
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struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
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shared_dpll[i] = pll->config;
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}
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}
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struct intel_shared_dpll_config *
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intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
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{
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struct intel_atomic_state *state = to_intel_atomic_state(s);
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WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
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if (!state->dpll_set) {
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state->dpll_set = true;
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intel_atomic_duplicate_dpll_state(to_i915(s->dev),
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state->shared_dpll);
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}
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return state->shared_dpll;
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}
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struct drm_atomic_state *
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intel_atomic_state_alloc(struct drm_device *dev)
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{
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struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
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kfree(state);
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return NULL;
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}
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return &state->base;
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}
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void intel_atomic_state_clear(struct drm_atomic_state *s)
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{
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struct intel_atomic_state *state = to_intel_atomic_state(s);
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drm_atomic_state_default_clear(&state->base);
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state->dpll_set = state->modeset = false;
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}
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