Vineet Gupta 55a2ae775a ARC: [arcompact] entry.S: Improve early return from exception ... The requirement is to - Reenable Exceptions (AE cleared) - Reenable Interrupts (E1/E2 set) We need to do wiggle these bits into ERSTATUS and call RTIE. Prev version used the pre-exception STATUS32 as starting point for what goes into ERSTATUS. This required explicit fixups of U/DE/L bits. Instead, use the current (in-exception) STATUS32 as starting point. Being in exception handler U/DE/L can be safely assumed to be correct. Only AE/E1/E2 need to be fixed. So the new implementation is slightly better -Avoids read form memory -Is 4 bytes smaller for the typical 1 level of intr configuration -Depicts the semantics more clearly Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-10-17 17:48:22 +05:30
..
arcregs.h	ARCv2: Support IO Coherency and permutations involving L1 and L2 caches	2015-08-20 18:11:17 +05:30
asm-offsets.h
atomic.h	Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2015-09-03 15:46:07 -07:00
barrier.h	ARCv2: barriers	2015-06-25 06:00:17 +05:30
bitops.h	ARC: Make ARC bitops "safer" (add anti-optimization)	2015-07-09 17:36:32 +05:30
bug.h
cache.h	ARCv2: Support IO Coherency and permutations involving L1 and L2 caches	2015-08-20 18:11:17 +05:30
cacheflush.h	ARC: fold ___flush_dcache_page into __flush_dcache_page	2015-05-19 11:27:13 +05:30
checksum.h
clk.h
cmpxchg.h	ARC: add/fix some comments in code - no functional change	2015-08-20 19:05:49 +05:30
current.h
delay.h	ARCv2: Adhere to Zero Delay loop restriction	2015-06-22 14:06:56 +05:30
disasm.h
dma-mapping.h	Merge branch 'akpm' (patches from Andrew)	2015-07-01 17:47:51 -07:00
dma.h
elf.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
entry-arcv2.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
entry-compact.h	ARC: [arcompact] entry.S: Improve early return from exception	2015-10-17 17:48:22 +05:30
entry.h	ARCv2: STAR 9000808988: signals involving Delay Slot	2015-06-22 14:06:55 +05:30
exec.h
futex.h	ARC: change some branchs to jumps to resolve linkage errors	2015-08-20 18:53:15 +05:30
hugepage.h	ARCv2: mm: THP: Implement flush_pmd_tlb_range() optimization	2015-10-17 17:48:21 +05:30
io.h	- Support for HS38 cores based on ARCv2 ISA	2015-07-01 09:24:26 -07:00
irq.h	ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al	2015-06-22 14:06:56 +05:30
irqflags-arcv2.h	ARCv2: STAR 9000814690: Really Re-enable interrupts to avoid deadlocks	2015-06-22 14:06:55 +05:30
irqflags-compact.h	ARC: [arcompact] entry.S: Improve early return from exception	2015-10-17 17:48:22 +05:30
irqflags.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
Kbuild	Merge branch 'strscpy' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile	2015-10-04 16:31:13 +01:00
kdebug.h
kgdb.h
kprobes.h
linkage.h
mach_desc.h
mcip.h	ARCv2: SMP: clocksource: Enable Global Real Time counter	2015-06-22 14:06:57 +05:30
mmu.h	ARCv2: MMUv4: TLB programming Model changes	2015-06-22 14:06:55 +05:30
mmu_context.h
module.h
mutex.h
page.h	ARCv2: mm: THP support	2015-10-17 17:48:18 +05:30
perf_event.h	ARCv2: perf: Finally introduce HS perf unit	2015-08-27 14:59:07 +05:30
pgalloc.h	ARC: mm: switch pgtable_to to pte_t *	2015-10-09 17:04:22 +05:30
pgtable.h	ARCv2: mm: THP support	2015-10-17 17:48:18 +05:30
processor.h	ARC: mm: document system mem map clearly	2015-06-19 18:09:29 +05:30
ptrace.h	ARC: Make pt_regs regs unsigned	2015-08-05 11:48:21 +05:30
sections.h
segment.h
serial.h	ARC: Dynamically determine BASE_BAUD from DeviceTree	2015-02-02 17:08:37 +05:30
setup.h
shmparam.h
smp.h
spinlock.h	ARCv2: spinlock/rwlock/atomics: reduce 1 instruction in exponential backoff	2015-08-07 13:56:16 +05:30
spinlock_types.h	ARC: LLOCK/SCOND based rwlock	2015-08-04 09:26:33 +05:30
stacktrace.h	ARC: Make arc_unwind_core accessible externally	2015-02-27 10:15:00 +05:30
string.h
switch_to.h
syscall.h
syscalls.h
thread_info.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
timex.h
tlb-mmu1.h
tlb.h
tlbflush.h	ARCv2: mm: THP: flush_pmd_tlb_range make SMP safe	2015-10-17 17:48:21 +05:30
uaccess.h	ARCv2: Adhere to Zero Delay loop restriction	2015-06-22 14:06:56 +05:30
unaligned.h
unwind.h