ef347c0cfd
The gpmi driver performance suffers from NAND operations being split in multiple small DMA transfers. This has been forced by the NAND layer in the former days, but now with exec_op we can use the controller as intended. With this patch gpmi_nfc_exec_op becomes the main entry point to NAND operations. Here all instructions are collected and chained as separate DMA transfers. In the end whole chain is fired and waited to be finished. gpmi_nfc_exec_op only does the hardware operations, bad block marker swapping and buffer scrambling is done by the callers. It's worth noting that the nand_*_op functions always take the buffer lengths for the data that the NAND chip actually transfers. When doing BCH we have to calculate the net data size from the raw data size in some places. This patch has been tested with 2048/64 and 2048/128 byte NAND on i.MX6q. mtd_oobtest, mtd_subpagetest and mtd_speedtest run without errors. nandbiterrs, nandpagetest and nandsubpagetest userspace tests from mtdutils run without errors and UBIFS can successfully be mounted. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
25 lines
798 B
C
25 lines
798 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _MXS_DMA_H_
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#define _MXS_DMA_H_
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#include <linux/dmaengine.h>
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#define MXS_DMA_CTRL_WAIT4END BIT(31)
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#define MXS_DMA_CTRL_WAIT4RDY BIT(30)
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/*
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* The mxs dmaengine can do PIO transfers. We pass a pointer to the PIO words
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* in the second argument to dmaengine_prep_slave_sg when the direction is
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* set to DMA_TRANS_NONE. To make this clear and to prevent users from doing
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* the error prone casting we have this wrapper function
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*/
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static inline struct dma_async_tx_descriptor *mxs_dmaengine_prep_pio(
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struct dma_chan *chan, u32 *pio, unsigned int npio,
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enum dma_transfer_direction dir, unsigned long flags)
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{
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return dmaengine_prep_slave_sg(chan, (struct scatterlist *)pio, npio,
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dir, flags);
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}
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#endif /* _MXS_DMA_H_ */
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