25f1ca31e2
This driver only creates a bunch of platform devices sharing resources belonging to the PMC device. This is pretty much what MFD subsystem is for so move the driver there, renaming it to intel_pmc_bxt.c which should be more clear what it is. MFD subsystem provides nice helper APIs for subdevice creation so convert the driver to use those. Unfortunately the ACPI device includes separate resources for most of the subdevices so we cannot simply call mfd_add_devices() to create all of them but instead we need to call it separately for each device. The new MFD driver continues to expose two sysfs attributes that allow userspace to send IPC commands to the PMC/SCU to avoid breaking any existing applications that may use these. Generally this is bad idea so document this in the ABI documentation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef MFD_INTEL_PMC_BXT_H
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#define MFD_INTEL_PMC_BXT_H
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/* GCR reg offsets from GCR base */
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#define PMC_GCR_PMC_CFG_REG 0x08
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#define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78
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#define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80
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/* PMC_CFG_REG bit masks */
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#define PMC_CFG_NO_REBOOT_EN BIT(4)
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/**
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* struct intel_pmc_dev - Intel PMC device structure
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* @dev: Pointer to the parent PMC device
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* @scu: Pointer to the SCU IPC device data structure
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* @gcr_mem_base: Virtual base address of GCR (Global Configuration Registers)
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* @gcr_lock: Lock used to serialize access to GCR registers
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* @telem_base: Pointer to telemetry SSRAM base resource or %NULL if not
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* available
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*/
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struct intel_pmc_dev {
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struct device *dev;
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struct intel_scu_ipc_dev *scu;
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void __iomem *gcr_mem_base;
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spinlock_t gcr_lock;
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struct resource *telem_base;
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};
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#if IS_ENABLED(CONFIG_MFD_INTEL_PMC_BXT)
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int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data);
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int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val);
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int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data);
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#else
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static inline int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset,
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u64 *data)
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{
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return -ENOTSUPP;
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}
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static inline int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset,
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u32 mask, u32 val)
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{
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return -ENOTSUPP;
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}
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static inline int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data)
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{
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return -ENOTSUPP;
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}
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#endif
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#endif /* MFD_INTEL_PMC_BXT_H */
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