2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
3809 lines
149 KiB
C
3809 lines
149 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* TI Palmas
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*
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* Copyright 2011-2013 Texas Instruments Inc.
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*
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* Author: Graeme Gregory <gg@slimlogic.co.uk>
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* Author: Ian Lartey <ian@slimlogic.co.uk>
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*/
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#ifndef __LINUX_MFD_PALMAS_H
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#define __LINUX_MFD_PALMAS_H
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#include <linux/usb/otg.h>
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#include <linux/leds.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/extcon-provider.h>
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#include <linux/of_gpio.h>
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#include <linux/usb/phy_companion.h>
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#define PALMAS_NUM_CLIENTS 3
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/* The ID_REVISION NUMBERS */
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#define PALMAS_CHIP_OLD_ID 0x0000
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#define PALMAS_CHIP_ID 0xC035
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#define PALMAS_CHIP_CHARGER_ID 0xC036
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#define TPS65917_RESERVED -1
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#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
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((a) == PALMAS_CHIP_ID))
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#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
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/**
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* Palmas PMIC feature types
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*
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* PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
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* regulator.
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*
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* PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
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* specific feature (above) or not. Return non-zero, if yes.
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*/
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#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
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#define PALMAS_PMIC_HAS(b, f) \
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((b)->features & PALMAS_PMIC_FEATURE_ ## f)
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struct palmas_pmic;
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struct palmas_gpadc;
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struct palmas_resource;
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struct palmas_usb;
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struct palmas_pmic_driver_data;
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struct palmas_pmic_platform_data;
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enum palmas_usb_state {
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PALMAS_USB_STATE_DISCONNECT,
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PALMAS_USB_STATE_VBUS,
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PALMAS_USB_STATE_ID,
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};
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struct palmas {
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struct device *dev;
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struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
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struct regmap *regmap[PALMAS_NUM_CLIENTS];
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/* Stored chip id */
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int id;
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unsigned int features;
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/* IRQ Data */
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int irq;
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u32 irq_mask;
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struct mutex irq_lock;
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struct regmap_irq_chip_data *irq_data;
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struct palmas_pmic_driver_data *pmic_ddata;
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/* Child Devices */
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struct palmas_pmic *pmic;
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struct palmas_gpadc *gpadc;
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struct palmas_resource *resource;
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struct palmas_usb *usb;
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/* GPIO MUXing */
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u8 gpio_muxed;
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u8 led_muxed;
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u8 pwm_muxed;
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};
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#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
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PALMAS_EXT_CONTROL_ENABLE2 | \
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PALMAS_EXT_CONTROL_NSLEEP)
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struct palmas_sleep_requestor_info {
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int id;
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int reg_offset;
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int bit_pos;
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};
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struct palmas_regs_info {
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char *name;
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char *sname;
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u8 vsel_addr;
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u8 ctrl_addr;
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u8 tstep_addr;
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int sleep_id;
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};
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struct palmas_pmic_driver_data {
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int smps_start;
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int smps_end;
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int ldo_begin;
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int ldo_end;
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int max_reg;
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bool has_regen3;
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struct palmas_regs_info *palmas_regs_info;
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struct of_regulator_match *palmas_matches;
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struct palmas_sleep_requestor_info *sleep_req_info;
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int (*smps_register)(struct palmas_pmic *pmic,
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struct palmas_pmic_driver_data *ddata,
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struct palmas_pmic_platform_data *pdata,
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const char *pdev_name,
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struct regulator_config config);
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int (*ldo_register)(struct palmas_pmic *pmic,
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struct palmas_pmic_driver_data *ddata,
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struct palmas_pmic_platform_data *pdata,
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const char *pdev_name,
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struct regulator_config config);
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};
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struct palmas_adc_wakeup_property {
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int adc_channel_number;
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int adc_high_threshold;
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int adc_low_threshold;
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};
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struct palmas_gpadc_platform_data {
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/* Channel 3 current source is only enabled during conversion */
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int ch3_current; /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */
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/* Channel 0 current source can be used for battery detection.
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* If used for battery detection this will cause a permanent current
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* consumption depending on current level set here.
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*/
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int ch0_current; /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */
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bool extended_delay; /* use extended delay for conversion */
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/* default BAT_REMOVAL_DAT setting on device probe */
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int bat_removal;
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/* Sets the START_POLARITY bit in the RT_CTRL register */
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int start_polarity;
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int auto_conversion_period_ms;
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struct palmas_adc_wakeup_property *adc_wakeup1_data;
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struct palmas_adc_wakeup_property *adc_wakeup2_data;
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};
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struct palmas_reg_init {
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/* warm_rest controls the voltage levels after a warm reset
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*
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* 0: reload default values from OTP on warm reset
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* 1: maintain voltage from VSEL on warm reset
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*/
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int warm_reset;
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/* roof_floor controls whether the regulator uses the i2c style
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* of DVS or uses the method where a GPIO or other control method is
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* attached to the NSLEEP/ENABLE1/ENABLE2 pins
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*
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* For SMPS
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*
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* 0: i2c selection of voltage
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* 1: pin selection of voltage.
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*
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* For LDO unused
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*/
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int roof_floor;
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/* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
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* the data sheet.
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*
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* For SMPS
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*
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* 0: Off
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* 1: AUTO
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* 2: ECO
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* 3: Forced PWM
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*
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* For LDO
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*
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* 0: Off
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* 1: On
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*/
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int mode_sleep;
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/* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
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* register. Set this is the default voltage set in OTP needs
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* to be overridden.
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*/
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u8 vsel;
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};
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enum palmas_regulators {
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/* SMPS regulators */
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PALMAS_REG_SMPS12,
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PALMAS_REG_SMPS123,
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PALMAS_REG_SMPS3,
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PALMAS_REG_SMPS45,
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PALMAS_REG_SMPS457,
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PALMAS_REG_SMPS6,
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PALMAS_REG_SMPS7,
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PALMAS_REG_SMPS8,
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PALMAS_REG_SMPS9,
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PALMAS_REG_SMPS10_OUT2,
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PALMAS_REG_SMPS10_OUT1,
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/* LDO regulators */
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PALMAS_REG_LDO1,
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PALMAS_REG_LDO2,
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PALMAS_REG_LDO3,
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PALMAS_REG_LDO4,
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PALMAS_REG_LDO5,
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PALMAS_REG_LDO6,
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PALMAS_REG_LDO7,
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PALMAS_REG_LDO8,
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PALMAS_REG_LDO9,
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PALMAS_REG_LDOLN,
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PALMAS_REG_LDOUSB,
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/* External regulators */
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PALMAS_REG_REGEN1,
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PALMAS_REG_REGEN2,
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PALMAS_REG_REGEN3,
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PALMAS_REG_SYSEN1,
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PALMAS_REG_SYSEN2,
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/* Total number of regulators */
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PALMAS_NUM_REGS,
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};
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enum tps65917_regulators {
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/* SMPS regulators */
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TPS65917_REG_SMPS1,
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TPS65917_REG_SMPS2,
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TPS65917_REG_SMPS3,
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TPS65917_REG_SMPS4,
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TPS65917_REG_SMPS5,
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TPS65917_REG_SMPS12,
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/* LDO regulators */
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TPS65917_REG_LDO1,
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TPS65917_REG_LDO2,
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TPS65917_REG_LDO3,
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TPS65917_REG_LDO4,
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TPS65917_REG_LDO5,
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TPS65917_REG_REGEN1,
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TPS65917_REG_REGEN2,
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TPS65917_REG_REGEN3,
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/* Total number of regulators */
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TPS65917_NUM_REGS,
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};
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/* External controll signal name */
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enum {
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PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
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PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
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PALMAS_EXT_CONTROL_NSLEEP = 0x4,
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};
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/*
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* Palmas device resources can be controlled externally for
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* enabling/disabling it rather than register write through i2c.
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* Add the external controlled requestor ID for different resources.
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*/
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enum palmas_external_requestor_id {
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PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
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PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
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PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
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PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
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PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
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PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
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PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
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PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
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PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
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PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
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PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
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PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
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PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
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PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
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PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
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PALMAS_EXTERNAL_REQSTR_ID_LDO1,
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PALMAS_EXTERNAL_REQSTR_ID_LDO2,
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PALMAS_EXTERNAL_REQSTR_ID_LDO3,
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PALMAS_EXTERNAL_REQSTR_ID_LDO4,
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PALMAS_EXTERNAL_REQSTR_ID_LDO5,
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PALMAS_EXTERNAL_REQSTR_ID_LDO6,
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PALMAS_EXTERNAL_REQSTR_ID_LDO7,
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PALMAS_EXTERNAL_REQSTR_ID_LDO8,
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PALMAS_EXTERNAL_REQSTR_ID_LDO9,
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PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
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PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
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/* Last entry */
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PALMAS_EXTERNAL_REQSTR_ID_MAX,
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};
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enum tps65917_external_requestor_id {
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TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
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TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
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TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
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TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
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TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
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TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
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TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
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TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
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TPS65917_EXTERNAL_REQSTR_ID_SMPS12,
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TPS65917_EXTERNAL_REQSTR_ID_LDO1,
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TPS65917_EXTERNAL_REQSTR_ID_LDO2,
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TPS65917_EXTERNAL_REQSTR_ID_LDO3,
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TPS65917_EXTERNAL_REQSTR_ID_LDO4,
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TPS65917_EXTERNAL_REQSTR_ID_LDO5,
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/* Last entry */
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TPS65917_EXTERNAL_REQSTR_ID_MAX,
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};
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struct palmas_pmic_platform_data {
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/* An array of pointers to regulator init data indexed by regulator
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* ID
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*/
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struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
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/* An array of pointers to structures containing sleep mode and DVS
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* configuration for regulators indexed by ID
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*/
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struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
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/* use LDO6 for vibrator control */
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int ldo6_vibrator;
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/* Enable tracking mode of LDO8 */
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bool enable_ldo8_tracking;
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};
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struct palmas_usb_platform_data {
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/* Do we enable the wakeup comparator on probe */
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int wakeup;
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};
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struct palmas_resource_platform_data {
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int regen1_mode_sleep;
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int regen2_mode_sleep;
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int sysen1_mode_sleep;
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int sysen2_mode_sleep;
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/* bitfield to be loaded to NSLEEP_RES_ASSIGN */
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u8 nsleep_res;
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/* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
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u8 nsleep_smps;
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/* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
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u8 nsleep_ldo1;
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/* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
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u8 nsleep_ldo2;
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/* bitfield to be loaded to ENABLE1_RES_ASSIGN */
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u8 enable1_res;
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/* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
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u8 enable1_smps;
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/* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
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u8 enable1_ldo1;
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/* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
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u8 enable1_ldo2;
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/* bitfield to be loaded to ENABLE2_RES_ASSIGN */
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u8 enable2_res;
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/* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
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u8 enable2_smps;
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/* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
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u8 enable2_ldo1;
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/* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
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u8 enable2_ldo2;
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};
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struct palmas_clk_platform_data {
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int clk32kg_mode_sleep;
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int clk32kgaudio_mode_sleep;
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};
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struct palmas_platform_data {
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int irq_flags;
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int gpio_base;
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/* bit value to be loaded to the POWER_CTRL register */
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u8 power_ctrl;
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/*
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* boolean to select if we want to configure muxing here
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* then the two value to load into the registers if true
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*/
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int mux_from_pdata;
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u8 pad1, pad2;
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bool pm_off;
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struct palmas_pmic_platform_data *pmic_pdata;
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struct palmas_gpadc_platform_data *gpadc_pdata;
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struct palmas_usb_platform_data *usb_pdata;
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struct palmas_resource_platform_data *resource_pdata;
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struct palmas_clk_platform_data *clk_pdata;
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};
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struct palmas_gpadc_calibration {
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s32 gain;
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s32 gain_error;
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s32 offset_error;
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};
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#define PALMAS_DATASHEET_NAME(_name) "palmas-gpadc-chan-"#_name
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struct palmas_gpadc_result {
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s32 raw_code;
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s32 corrected_code;
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s32 result;
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};
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#define PALMAS_MAX_CHANNELS 16
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/* Define the tps65917 IRQ numbers */
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enum tps65917_irqs {
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/* INT1 registers */
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TPS65917_RESERVED1,
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TPS65917_PWRON_IRQ,
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TPS65917_LONG_PRESS_KEY_IRQ,
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TPS65917_RESERVED2,
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TPS65917_PWRDOWN_IRQ,
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TPS65917_HOTDIE_IRQ,
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TPS65917_VSYS_MON_IRQ,
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TPS65917_RESERVED3,
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/* INT2 registers */
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TPS65917_RESERVED4,
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TPS65917_OTP_ERROR_IRQ,
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TPS65917_WDT_IRQ,
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TPS65917_RESERVED5,
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TPS65917_RESET_IN_IRQ,
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TPS65917_FSD_IRQ,
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TPS65917_SHORT_IRQ,
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TPS65917_RESERVED6,
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/* INT3 registers */
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TPS65917_GPADC_AUTO_0_IRQ,
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TPS65917_GPADC_AUTO_1_IRQ,
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TPS65917_GPADC_EOC_SW_IRQ,
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TPS65917_RESREVED6,
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TPS65917_RESERVED7,
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TPS65917_RESERVED8,
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TPS65917_RESERVED9,
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TPS65917_VBUS_IRQ,
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/* INT4 registers */
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TPS65917_GPIO_0_IRQ,
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TPS65917_GPIO_1_IRQ,
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TPS65917_GPIO_2_IRQ,
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TPS65917_GPIO_3_IRQ,
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TPS65917_GPIO_4_IRQ,
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TPS65917_GPIO_5_IRQ,
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TPS65917_GPIO_6_IRQ,
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TPS65917_RESERVED10,
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/* Total Number IRQs */
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TPS65917_NUM_IRQ,
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};
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/* Define the palmas IRQ numbers */
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enum palmas_irqs {
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/* INT1 registers */
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PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
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PALMAS_PWRON_IRQ,
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|
PALMAS_LONG_PRESS_KEY_IRQ,
|
|
PALMAS_RPWRON_IRQ,
|
|
PALMAS_PWRDOWN_IRQ,
|
|
PALMAS_HOTDIE_IRQ,
|
|
PALMAS_VSYS_MON_IRQ,
|
|
PALMAS_VBAT_MON_IRQ,
|
|
/* INT2 registers */
|
|
PALMAS_RTC_ALARM_IRQ,
|
|
PALMAS_RTC_TIMER_IRQ,
|
|
PALMAS_WDT_IRQ,
|
|
PALMAS_BATREMOVAL_IRQ,
|
|
PALMAS_RESET_IN_IRQ,
|
|
PALMAS_FBI_BB_IRQ,
|
|
PALMAS_SHORT_IRQ,
|
|
PALMAS_VAC_ACOK_IRQ,
|
|
/* INT3 registers */
|
|
PALMAS_GPADC_AUTO_0_IRQ,
|
|
PALMAS_GPADC_AUTO_1_IRQ,
|
|
PALMAS_GPADC_EOC_SW_IRQ,
|
|
PALMAS_GPADC_EOC_RT_IRQ,
|
|
PALMAS_ID_OTG_IRQ,
|
|
PALMAS_ID_IRQ,
|
|
PALMAS_VBUS_OTG_IRQ,
|
|
PALMAS_VBUS_IRQ,
|
|
/* INT4 registers */
|
|
PALMAS_GPIO_0_IRQ,
|
|
PALMAS_GPIO_1_IRQ,
|
|
PALMAS_GPIO_2_IRQ,
|
|
PALMAS_GPIO_3_IRQ,
|
|
PALMAS_GPIO_4_IRQ,
|
|
PALMAS_GPIO_5_IRQ,
|
|
PALMAS_GPIO_6_IRQ,
|
|
PALMAS_GPIO_7_IRQ,
|
|
/* Total Number IRQs */
|
|
PALMAS_NUM_IRQ,
|
|
};
|
|
|
|
/* Palmas GPADC Channels */
|
|
enum {
|
|
PALMAS_ADC_CH_IN0,
|
|
PALMAS_ADC_CH_IN1,
|
|
PALMAS_ADC_CH_IN2,
|
|
PALMAS_ADC_CH_IN3,
|
|
PALMAS_ADC_CH_IN4,
|
|
PALMAS_ADC_CH_IN5,
|
|
PALMAS_ADC_CH_IN6,
|
|
PALMAS_ADC_CH_IN7,
|
|
PALMAS_ADC_CH_IN8,
|
|
PALMAS_ADC_CH_IN9,
|
|
PALMAS_ADC_CH_IN10,
|
|
PALMAS_ADC_CH_IN11,
|
|
PALMAS_ADC_CH_IN12,
|
|
PALMAS_ADC_CH_IN13,
|
|
PALMAS_ADC_CH_IN14,
|
|
PALMAS_ADC_CH_IN15,
|
|
PALMAS_ADC_CH_MAX,
|
|
};
|
|
|
|
/* Palmas GPADC Channel0 Current Source */
|
|
enum {
|
|
PALMAS_ADC_CH0_CURRENT_SRC_0,
|
|
PALMAS_ADC_CH0_CURRENT_SRC_5,
|
|
PALMAS_ADC_CH0_CURRENT_SRC_15,
|
|
PALMAS_ADC_CH0_CURRENT_SRC_20,
|
|
};
|
|
|
|
/* Palmas GPADC Channel3 Current Source */
|
|
enum {
|
|
PALMAS_ADC_CH3_CURRENT_SRC_0,
|
|
PALMAS_ADC_CH3_CURRENT_SRC_10,
|
|
PALMAS_ADC_CH3_CURRENT_SRC_400,
|
|
PALMAS_ADC_CH3_CURRENT_SRC_800,
|
|
};
|
|
|
|
struct palmas_pmic {
|
|
struct palmas *palmas;
|
|
struct device *dev;
|
|
struct regulator_desc desc[PALMAS_NUM_REGS];
|
|
struct mutex mutex;
|
|
|
|
int smps123;
|
|
int smps457;
|
|
int smps12;
|
|
|
|
int range[PALMAS_REG_SMPS10_OUT1];
|
|
unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
|
|
unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
|
|
};
|
|
|
|
struct palmas_resource {
|
|
struct palmas *palmas;
|
|
struct device *dev;
|
|
};
|
|
|
|
struct palmas_usb {
|
|
struct palmas *palmas;
|
|
struct device *dev;
|
|
|
|
struct extcon_dev *edev;
|
|
|
|
int id_otg_irq;
|
|
int id_irq;
|
|
int vbus_otg_irq;
|
|
int vbus_irq;
|
|
|
|
int gpio_id_irq;
|
|
int gpio_vbus_irq;
|
|
struct gpio_desc *id_gpiod;
|
|
struct gpio_desc *vbus_gpiod;
|
|
unsigned long sw_debounce_jiffies;
|
|
struct delayed_work wq_detectid;
|
|
|
|
enum palmas_usb_state linkstat;
|
|
int wakeup;
|
|
bool enable_vbus_detection;
|
|
bool enable_id_detection;
|
|
bool enable_gpio_id_detection;
|
|
bool enable_gpio_vbus_detection;
|
|
};
|
|
|
|
#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
|
|
|
|
enum usb_irq_events {
|
|
/* Wakeup events from INT3 */
|
|
PALMAS_USB_ID_WAKEPUP,
|
|
PALMAS_USB_VBUS_WAKEUP,
|
|
|
|
/* ID_OTG_EVENTS */
|
|
PALMAS_USB_ID_GND,
|
|
N_PALMAS_USB_ID_GND,
|
|
PALMAS_USB_ID_C,
|
|
N_PALMAS_USB_ID_C,
|
|
PALMAS_USB_ID_B,
|
|
N_PALMAS_USB_ID_B,
|
|
PALMAS_USB_ID_A,
|
|
N_PALMAS_USB_ID_A,
|
|
PALMAS_USB_ID_FLOAT,
|
|
N_PALMAS_USB_ID_FLOAT,
|
|
|
|
/* VBUS_OTG_EVENTS */
|
|
PALMAS_USB_VB_SESS_END,
|
|
N_PALMAS_USB_VB_SESS_END,
|
|
PALMAS_USB_VB_SESS_VLD,
|
|
N_PALMAS_USB_VB_SESS_VLD,
|
|
PALMAS_USB_VA_SESS_VLD,
|
|
N_PALMAS_USB_VA_SESS_VLD,
|
|
PALMAS_USB_VA_VBUS_VLD,
|
|
N_PALMAS_USB_VA_VBUS_VLD,
|
|
PALMAS_USB_VADP_SNS,
|
|
N_PALMAS_USB_VADP_SNS,
|
|
PALMAS_USB_VADP_PRB,
|
|
N_PALMAS_USB_VADP_PRB,
|
|
PALMAS_USB_VOTG_SESS_VLD,
|
|
N_PALMAS_USB_VOTG_SESS_VLD,
|
|
};
|
|
|
|
/* defines so we can store the mux settings */
|
|
#define PALMAS_GPIO_0_MUXED (1 << 0)
|
|
#define PALMAS_GPIO_1_MUXED (1 << 1)
|
|
#define PALMAS_GPIO_2_MUXED (1 << 2)
|
|
#define PALMAS_GPIO_3_MUXED (1 << 3)
|
|
#define PALMAS_GPIO_4_MUXED (1 << 4)
|
|
#define PALMAS_GPIO_5_MUXED (1 << 5)
|
|
#define PALMAS_GPIO_6_MUXED (1 << 6)
|
|
#define PALMAS_GPIO_7_MUXED (1 << 7)
|
|
|
|
#define PALMAS_LED1_MUXED (1 << 0)
|
|
#define PALMAS_LED2_MUXED (1 << 1)
|
|
|
|
#define PALMAS_PWM1_MUXED (1 << 0)
|
|
#define PALMAS_PWM2_MUXED (1 << 1)
|
|
|
|
/* helper macro to get correct slave number */
|
|
#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
|
|
#define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
|
|
|
|
/* Base addresses of IP blocks in Palmas */
|
|
#define PALMAS_SMPS_DVS_BASE 0x020
|
|
#define PALMAS_RTC_BASE 0x100
|
|
#define PALMAS_VALIDITY_BASE 0x118
|
|
#define PALMAS_SMPS_BASE 0x120
|
|
#define PALMAS_LDO_BASE 0x150
|
|
#define PALMAS_DVFS_BASE 0x180
|
|
#define PALMAS_PMU_CONTROL_BASE 0x1A0
|
|
#define PALMAS_RESOURCE_BASE 0x1D4
|
|
#define PALMAS_PU_PD_OD_BASE 0x1F0
|
|
#define PALMAS_LED_BASE 0x200
|
|
#define PALMAS_INTERRUPT_BASE 0x210
|
|
#define PALMAS_USB_OTG_BASE 0x250
|
|
#define PALMAS_VIBRATOR_BASE 0x270
|
|
#define PALMAS_GPIO_BASE 0x280
|
|
#define PALMAS_USB_BASE 0x290
|
|
#define PALMAS_GPADC_BASE 0x2C0
|
|
#define PALMAS_TRIM_GPADC_BASE 0x3CD
|
|
|
|
/* Registers for function RTC */
|
|
#define PALMAS_SECONDS_REG 0x00
|
|
#define PALMAS_MINUTES_REG 0x01
|
|
#define PALMAS_HOURS_REG 0x02
|
|
#define PALMAS_DAYS_REG 0x03
|
|
#define PALMAS_MONTHS_REG 0x04
|
|
#define PALMAS_YEARS_REG 0x05
|
|
#define PALMAS_WEEKS_REG 0x06
|
|
#define PALMAS_ALARM_SECONDS_REG 0x08
|
|
#define PALMAS_ALARM_MINUTES_REG 0x09
|
|
#define PALMAS_ALARM_HOURS_REG 0x0A
|
|
#define PALMAS_ALARM_DAYS_REG 0x0B
|
|
#define PALMAS_ALARM_MONTHS_REG 0x0C
|
|
#define PALMAS_ALARM_YEARS_REG 0x0D
|
|
#define PALMAS_RTC_CTRL_REG 0x10
|
|
#define PALMAS_RTC_STATUS_REG 0x11
|
|
#define PALMAS_RTC_INTERRUPTS_REG 0x12
|
|
#define PALMAS_RTC_COMP_LSB_REG 0x13
|
|
#define PALMAS_RTC_COMP_MSB_REG 0x14
|
|
#define PALMAS_RTC_RES_PROG_REG 0x15
|
|
#define PALMAS_RTC_RESET_STATUS_REG 0x16
|
|
|
|
/* Bit definitions for SECONDS_REG */
|
|
#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
|
|
#define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
|
|
#define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
|
|
#define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
|
|
|
|
/* Bit definitions for MINUTES_REG */
|
|
#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
|
|
#define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
|
|
#define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
|
|
#define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
|
|
|
|
/* Bit definitions for HOURS_REG */
|
|
#define PALMAS_HOURS_REG_PM_NAM 0x80
|
|
#define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
|
|
#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
|
|
#define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
|
|
#define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
|
|
#define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
|
|
|
|
/* Bit definitions for DAYS_REG */
|
|
#define PALMAS_DAYS_REG_DAY1_MASK 0x30
|
|
#define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
|
|
#define PALMAS_DAYS_REG_DAY0_MASK 0x0F
|
|
#define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
|
|
|
|
/* Bit definitions for MONTHS_REG */
|
|
#define PALMAS_MONTHS_REG_MONTH1 0x10
|
|
#define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
|
|
#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
|
|
#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
|
|
|
|
/* Bit definitions for YEARS_REG */
|
|
#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
|
|
#define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
|
|
#define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
|
|
#define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
|
|
|
|
/* Bit definitions for WEEKS_REG */
|
|
#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
|
|
#define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
|
|
|
|
/* Bit definitions for ALARM_SECONDS_REG */
|
|
#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
|
|
#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
|
|
#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
|
|
#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
|
|
|
|
/* Bit definitions for ALARM_MINUTES_REG */
|
|
#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
|
|
#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
|
|
#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
|
|
#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
|
|
|
|
/* Bit definitions for ALARM_HOURS_REG */
|
|
#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
|
|
#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
|
|
#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
|
|
#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
|
|
#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
|
|
#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
|
|
|
|
/* Bit definitions for ALARM_DAYS_REG */
|
|
#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
|
|
#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
|
|
#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
|
|
#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
|
|
|
|
/* Bit definitions for ALARM_MONTHS_REG */
|
|
#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
|
|
#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
|
|
#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
|
|
#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
|
|
|
|
/* Bit definitions for ALARM_YEARS_REG */
|
|
#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
|
|
#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
|
|
#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
|
|
#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
|
|
|
|
/* Bit definitions for RTC_CTRL_REG */
|
|
#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
|
|
#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
|
|
#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
|
|
#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
|
|
#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
|
|
#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
|
|
#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
|
|
#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
|
|
#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
|
|
#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
|
|
#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
|
|
#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
|
|
#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
|
|
#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
|
|
#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
|
|
#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
|
|
|
|
/* Bit definitions for RTC_STATUS_REG */
|
|
#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
|
|
#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
|
|
#define PALMAS_RTC_STATUS_REG_ALARM 0x40
|
|
#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
|
|
#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
|
|
#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
|
|
#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
|
|
#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
|
|
#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
|
|
#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
|
|
#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
|
|
#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
|
|
#define PALMAS_RTC_STATUS_REG_RUN 0x02
|
|
#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
|
|
|
|
/* Bit definitions for RTC_INTERRUPTS_REG */
|
|
#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
|
|
#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
|
|
#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
|
|
#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
|
|
#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
|
|
#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
|
|
#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
|
|
#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
|
|
|
|
/* Bit definitions for RTC_COMP_LSB_REG */
|
|
#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
|
|
#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
|
|
|
|
/* Bit definitions for RTC_COMP_MSB_REG */
|
|
#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
|
|
#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
|
|
|
|
/* Bit definitions for RTC_RES_PROG_REG */
|
|
#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
|
|
#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
|
|
|
|
/* Bit definitions for RTC_RESET_STATUS_REG */
|
|
#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
|
|
#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
|
|
|
|
/* Registers for function BACKUP */
|
|
#define PALMAS_BACKUP0 0x00
|
|
#define PALMAS_BACKUP1 0x01
|
|
#define PALMAS_BACKUP2 0x02
|
|
#define PALMAS_BACKUP3 0x03
|
|
#define PALMAS_BACKUP4 0x04
|
|
#define PALMAS_BACKUP5 0x05
|
|
#define PALMAS_BACKUP6 0x06
|
|
#define PALMAS_BACKUP7 0x07
|
|
|
|
/* Bit definitions for BACKUP0 */
|
|
#define PALMAS_BACKUP0_BACKUP_MASK 0xFF
|
|
#define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
|
|
|
|
/* Bit definitions for BACKUP1 */
|
|
#define PALMAS_BACKUP1_BACKUP_MASK 0xFF
|
|
#define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
|
|
|
|
/* Bit definitions for BACKUP2 */
|
|
#define PALMAS_BACKUP2_BACKUP_MASK 0xFF
|
|
#define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
|
|
|
|
/* Bit definitions for BACKUP3 */
|
|
#define PALMAS_BACKUP3_BACKUP_MASK 0xFF
|
|
#define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
|
|
|
|
/* Bit definitions for BACKUP4 */
|
|
#define PALMAS_BACKUP4_BACKUP_MASK 0xFF
|
|
#define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
|
|
|
|
/* Bit definitions for BACKUP5 */
|
|
#define PALMAS_BACKUP5_BACKUP_MASK 0xFF
|
|
#define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
|
|
|
|
/* Bit definitions for BACKUP6 */
|
|
#define PALMAS_BACKUP6_BACKUP_MASK 0xFF
|
|
#define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
|
|
|
|
/* Bit definitions for BACKUP7 */
|
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#define PALMAS_BACKUP7_BACKUP_MASK 0xFF
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#define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
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/* Registers for function SMPS */
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#define PALMAS_SMPS12_CTRL 0x00
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#define PALMAS_SMPS12_TSTEP 0x01
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#define PALMAS_SMPS12_FORCE 0x02
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#define PALMAS_SMPS12_VOLTAGE 0x03
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#define PALMAS_SMPS3_CTRL 0x04
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#define PALMAS_SMPS3_VOLTAGE 0x07
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#define PALMAS_SMPS45_CTRL 0x08
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#define PALMAS_SMPS45_TSTEP 0x09
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#define PALMAS_SMPS45_FORCE 0x0A
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#define PALMAS_SMPS45_VOLTAGE 0x0B
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#define PALMAS_SMPS6_CTRL 0x0C
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#define PALMAS_SMPS6_TSTEP 0x0D
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#define PALMAS_SMPS6_FORCE 0x0E
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#define PALMAS_SMPS6_VOLTAGE 0x0F
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#define PALMAS_SMPS7_CTRL 0x10
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#define PALMAS_SMPS7_VOLTAGE 0x13
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#define PALMAS_SMPS8_CTRL 0x14
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#define PALMAS_SMPS8_TSTEP 0x15
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#define PALMAS_SMPS8_FORCE 0x16
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#define PALMAS_SMPS8_VOLTAGE 0x17
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#define PALMAS_SMPS9_CTRL 0x18
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#define PALMAS_SMPS9_VOLTAGE 0x1B
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#define PALMAS_SMPS10_CTRL 0x1C
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#define PALMAS_SMPS10_STATUS 0x1F
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#define PALMAS_SMPS_CTRL 0x24
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#define PALMAS_SMPS_PD_CTRL 0x25
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#define PALMAS_SMPS_DITHER_EN 0x26
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#define PALMAS_SMPS_THERMAL_EN 0x27
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#define PALMAS_SMPS_THERMAL_STATUS 0x28
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#define PALMAS_SMPS_SHORT_STATUS 0x29
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
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#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
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#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
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/* Bit definitions for SMPS12_CTRL */
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#define PALMAS_SMPS12_CTRL_WR_S 0x80
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#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
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#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
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#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
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#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
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#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
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#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for SMPS12_TSTEP */
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#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
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#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
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/* Bit definitions for SMPS12_FORCE */
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#define PALMAS_SMPS12_FORCE_CMD 0x80
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#define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
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#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
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#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS12_VOLTAGE */
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#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
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#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
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#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
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#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS3_CTRL */
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#define PALMAS_SMPS3_CTRL_WR_S 0x80
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#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
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#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
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#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
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#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for SMPS3_VOLTAGE */
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#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
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#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
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#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
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#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS45_CTRL */
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#define PALMAS_SMPS45_CTRL_WR_S 0x80
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#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
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#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
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#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
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#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
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#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
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#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for SMPS45_TSTEP */
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#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
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#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
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/* Bit definitions for SMPS45_FORCE */
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#define PALMAS_SMPS45_FORCE_CMD 0x80
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#define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
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#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
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#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS45_VOLTAGE */
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#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
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#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
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#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
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#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS6_CTRL */
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#define PALMAS_SMPS6_CTRL_WR_S 0x80
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#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
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#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
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#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
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#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
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#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
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#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for SMPS6_TSTEP */
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#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
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#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
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/* Bit definitions for SMPS6_FORCE */
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#define PALMAS_SMPS6_FORCE_CMD 0x80
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#define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
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#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
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#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS6_VOLTAGE */
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#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
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#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
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#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
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#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS7_CTRL */
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#define PALMAS_SMPS7_CTRL_WR_S 0x80
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#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
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#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
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#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
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#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for SMPS7_VOLTAGE */
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#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
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#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
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#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
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#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS8_CTRL */
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#define PALMAS_SMPS8_CTRL_WR_S 0x80
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#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
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#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
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#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
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#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
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#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
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#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for SMPS8_TSTEP */
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#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
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#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
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/* Bit definitions for SMPS8_FORCE */
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#define PALMAS_SMPS8_FORCE_CMD 0x80
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#define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
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#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
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#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS8_VOLTAGE */
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#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
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#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
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#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
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#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS9_CTRL */
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#define PALMAS_SMPS9_CTRL_WR_S 0x80
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#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
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#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
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#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
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#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for SMPS9_VOLTAGE */
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#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
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#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
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#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
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#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for SMPS10_CTRL */
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#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
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#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
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#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
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#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for SMPS10_STATUS */
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#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
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#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
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/* Bit definitions for SMPS_CTRL */
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#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
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#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
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#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
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#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
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#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
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#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
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#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
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#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
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/* Bit definitions for SMPS_PD_CTRL */
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#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
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#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
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#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
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#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
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#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
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#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
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#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
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#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
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#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
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#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
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#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
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#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
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#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
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#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
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/* Bit definitions for SMPS_THERMAL_EN */
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#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
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#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
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#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
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#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
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#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
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#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
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#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
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#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
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#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
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#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
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/* Bit definitions for SMPS_THERMAL_STATUS */
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
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#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
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/* Bit definitions for SMPS_SHORT_STATUS */
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#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
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#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
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#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
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#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
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#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
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#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
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#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
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#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
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#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
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#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
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#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
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#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
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#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
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#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
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#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
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#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
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/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
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#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
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/* Bit definitions for SMPS_POWERGOOD_MASK1 */
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
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#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
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/* Bit definitions for SMPS_POWERGOOD_MASK2 */
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#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
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#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
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#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
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#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
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#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
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#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
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#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
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#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
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/* Registers for function LDO */
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#define PALMAS_LDO1_CTRL 0x00
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#define PALMAS_LDO1_VOLTAGE 0x01
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#define PALMAS_LDO2_CTRL 0x02
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#define PALMAS_LDO2_VOLTAGE 0x03
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#define PALMAS_LDO3_CTRL 0x04
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#define PALMAS_LDO3_VOLTAGE 0x05
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#define PALMAS_LDO4_CTRL 0x06
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#define PALMAS_LDO4_VOLTAGE 0x07
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#define PALMAS_LDO5_CTRL 0x08
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#define PALMAS_LDO5_VOLTAGE 0x09
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#define PALMAS_LDO6_CTRL 0x0A
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#define PALMAS_LDO6_VOLTAGE 0x0B
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#define PALMAS_LDO7_CTRL 0x0C
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#define PALMAS_LDO7_VOLTAGE 0x0D
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#define PALMAS_LDO8_CTRL 0x0E
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#define PALMAS_LDO8_VOLTAGE 0x0F
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#define PALMAS_LDO9_CTRL 0x10
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#define PALMAS_LDO9_VOLTAGE 0x11
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#define PALMAS_LDOLN_CTRL 0x12
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#define PALMAS_LDOLN_VOLTAGE 0x13
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#define PALMAS_LDOUSB_CTRL 0x14
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#define PALMAS_LDOUSB_VOLTAGE 0x15
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#define PALMAS_LDO_CTRL 0x1A
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#define PALMAS_LDO_PD_CTRL1 0x1B
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#define PALMAS_LDO_PD_CTRL2 0x1C
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#define PALMAS_LDO_SHORT_STATUS1 0x1D
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#define PALMAS_LDO_SHORT_STATUS2 0x1E
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/* Bit definitions for LDO1_CTRL */
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#define PALMAS_LDO1_CTRL_WR_S 0x80
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#define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDO1_CTRL_STATUS 0x10
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#define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDO1_VOLTAGE */
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#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDO2_CTRL */
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#define PALMAS_LDO2_CTRL_WR_S 0x80
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#define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDO2_CTRL_STATUS 0x10
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#define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDO2_VOLTAGE */
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#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDO3_CTRL */
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#define PALMAS_LDO3_CTRL_WR_S 0x80
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#define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDO3_CTRL_STATUS 0x10
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#define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDO3_VOLTAGE */
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#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDO4_CTRL */
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#define PALMAS_LDO4_CTRL_WR_S 0x80
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#define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDO4_CTRL_STATUS 0x10
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#define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDO4_VOLTAGE */
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#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDO5_CTRL */
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#define PALMAS_LDO5_CTRL_WR_S 0x80
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#define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDO5_CTRL_STATUS 0x10
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#define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDO5_VOLTAGE */
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#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDO6_CTRL */
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#define PALMAS_LDO6_CTRL_WR_S 0x80
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#define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
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#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
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#define PALMAS_LDO6_CTRL_STATUS 0x10
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#define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDO6_VOLTAGE */
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#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDO7_CTRL */
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#define PALMAS_LDO7_CTRL_WR_S 0x80
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#define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDO7_CTRL_STATUS 0x10
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#define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDO7_VOLTAGE */
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#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDO8_CTRL */
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#define PALMAS_LDO8_CTRL_WR_S 0x80
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#define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
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#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
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#define PALMAS_LDO8_CTRL_STATUS 0x10
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#define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDO8_VOLTAGE */
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#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDO9_CTRL */
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#define PALMAS_LDO9_CTRL_WR_S 0x80
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#define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
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#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
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#define PALMAS_LDO9_CTRL_STATUS 0x10
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#define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDO9_VOLTAGE */
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#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDOLN_CTRL */
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#define PALMAS_LDOLN_CTRL_WR_S 0x80
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#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDOLN_CTRL_STATUS 0x10
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#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDOLN_VOLTAGE */
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#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDOUSB_CTRL */
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#define PALMAS_LDOUSB_CTRL_WR_S 0x80
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#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
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#define PALMAS_LDOUSB_CTRL_STATUS 0x10
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#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
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#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
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#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
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#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
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#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for LDOUSB_VOLTAGE */
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#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
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#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
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/* Bit definitions for LDO_CTRL */
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#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
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#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
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/* Bit definitions for LDO_PD_CTRL1 */
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#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
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#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
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#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
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#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
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#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
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#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
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#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
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#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
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#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
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#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
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#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
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#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
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#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
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#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
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#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
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#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
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/* Bit definitions for LDO_PD_CTRL2 */
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#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
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#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
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#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
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#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
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#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
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#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
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/* Bit definitions for LDO_SHORT_STATUS1 */
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#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
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#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
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#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
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#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
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#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
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#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
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#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
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#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
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#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
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#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
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#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
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#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
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#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
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#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
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#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
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#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
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/* Bit definitions for LDO_SHORT_STATUS2 */
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#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
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#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
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#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
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#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
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#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
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#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
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#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
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#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
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/* Registers for function PMU_CONTROL */
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#define PALMAS_DEV_CTRL 0x00
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#define PALMAS_POWER_CTRL 0x01
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#define PALMAS_VSYS_LO 0x02
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#define PALMAS_VSYS_MON 0x03
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#define PALMAS_VBAT_MON 0x04
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#define PALMAS_WATCHDOG 0x05
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#define PALMAS_BOOT_STATUS 0x06
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#define PALMAS_BATTERY_BOUNCE 0x07
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#define PALMAS_BACKUP_BATTERY_CTRL 0x08
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#define PALMAS_LONG_PRESS_KEY 0x09
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#define PALMAS_OSC_THERM_CTRL 0x0A
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#define PALMAS_BATDEBOUNCING 0x0B
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#define PALMAS_SWOFF_HWRST 0x0F
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#define PALMAS_SWOFF_COLDRST 0x10
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#define PALMAS_SWOFF_STATUS 0x11
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#define PALMAS_PMU_CONFIG 0x12
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#define PALMAS_SPARE 0x14
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#define PALMAS_PMU_SECONDARY_INT 0x15
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#define PALMAS_SW_REVISION 0x17
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#define PALMAS_EXT_CHRG_CTRL 0x18
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#define PALMAS_PMU_SECONDARY_INT2 0x19
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/* Bit definitions for DEV_CTRL */
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#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
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#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
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#define PALMAS_DEV_CTRL_SW_RST 0x02
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#define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
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#define PALMAS_DEV_CTRL_DEV_ON 0x01
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#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
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/* Bit definitions for POWER_CTRL */
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#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
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#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
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#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
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#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
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#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
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#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
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/* Bit definitions for VSYS_LO */
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#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
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#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
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/* Bit definitions for VSYS_MON */
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#define PALMAS_VSYS_MON_ENABLE 0x80
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#define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
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#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
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#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
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/* Bit definitions for VBAT_MON */
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#define PALMAS_VBAT_MON_ENABLE 0x80
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#define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
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#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
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#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
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/* Bit definitions for WATCHDOG */
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#define PALMAS_WATCHDOG_LOCK 0x20
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#define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
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#define PALMAS_WATCHDOG_ENABLE 0x10
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#define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
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#define PALMAS_WATCHDOG_MODE 0x08
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#define PALMAS_WATCHDOG_MODE_SHIFT 0x03
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#define PALMAS_WATCHDOG_TIMER_MASK 0x07
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#define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
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/* Bit definitions for BOOT_STATUS */
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#define PALMAS_BOOT_STATUS_BOOT1 0x02
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#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
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#define PALMAS_BOOT_STATUS_BOOT0 0x01
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#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
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/* Bit definitions for BATTERY_BOUNCE */
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#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
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#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
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/* Bit definitions for BACKUP_BATTERY_CTRL */
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#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
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#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
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#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
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#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
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#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
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#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
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#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
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#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
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#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
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#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
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#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
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#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
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#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
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#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
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/* Bit definitions for LONG_PRESS_KEY */
|
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#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
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#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
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#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
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#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
|
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#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
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#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
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#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
|
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#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
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|
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/* Bit definitions for OSC_THERM_CTRL */
|
|
#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
|
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#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
|
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#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
|
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#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
|
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#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
|
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#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
|
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#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
|
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#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
|
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#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
|
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#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
|
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#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
|
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#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
|
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#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
|
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#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
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|
|
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/* Bit definitions for BATDEBOUNCING */
|
|
#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
|
|
#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
|
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#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
|
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#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
|
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#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
|
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#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
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|
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/* Bit definitions for SWOFF_HWRST */
|
|
#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
|
|
#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
|
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#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
|
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#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
|
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#define PALMAS_SWOFF_HWRST_WTD 0x20
|
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#define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
|
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#define PALMAS_SWOFF_HWRST_TSHUT 0x10
|
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#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
|
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#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
|
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#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
|
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#define PALMAS_SWOFF_HWRST_SW_RST 0x04
|
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#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
|
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#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
|
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#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
|
|
#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
|
|
#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
|
|
|
|
/* Bit definitions for SWOFF_COLDRST */
|
|
#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
|
|
#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
|
|
#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
|
|
#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
|
|
#define PALMAS_SWOFF_COLDRST_WTD 0x20
|
|
#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
|
|
#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
|
|
#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
|
|
#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
|
|
#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
|
|
#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
|
|
#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
|
|
#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
|
|
#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
|
|
#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
|
|
#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
|
|
|
|
/* Bit definitions for SWOFF_STATUS */
|
|
#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
|
|
#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
|
|
#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
|
|
#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
|
|
#define PALMAS_SWOFF_STATUS_WTD 0x20
|
|
#define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
|
|
#define PALMAS_SWOFF_STATUS_TSHUT 0x10
|
|
#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
|
|
#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
|
|
#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
|
|
#define PALMAS_SWOFF_STATUS_SW_RST 0x04
|
|
#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
|
|
#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
|
|
#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
|
|
#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
|
|
#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
|
|
|
|
/* Bit definitions for PMU_CONFIG */
|
|
#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
|
|
#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
|
|
#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
|
|
#define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
|
|
#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
|
|
#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
|
|
#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
|
|
#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
|
|
#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
|
|
#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
|
|
|
|
/* Bit definitions for SPARE */
|
|
#define PALMAS_SPARE_SPARE_MASK 0xf8
|
|
#define PALMAS_SPARE_SPARE_SHIFT 0x03
|
|
#define PALMAS_SPARE_REGEN3_OD 0x04
|
|
#define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
|
|
#define PALMAS_SPARE_REGEN2_OD 0x02
|
|
#define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
|
|
#define PALMAS_SPARE_REGEN1_OD 0x01
|
|
#define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
|
|
|
|
/* Bit definitions for PMU_SECONDARY_INT */
|
|
#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
|
|
#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
|
|
#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
|
|
#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
|
|
#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
|
|
#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
|
|
#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
|
|
#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
|
|
#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
|
|
#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
|
|
#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
|
|
#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
|
|
#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
|
|
#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
|
|
#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
|
|
#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
|
|
|
|
/* Bit definitions for SW_REVISION */
|
|
#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
|
|
#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
|
|
|
|
/* Bit definitions for EXT_CHRG_CTRL */
|
|
#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
|
|
#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
|
|
#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
|
|
#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
|
|
#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
|
|
#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
|
|
#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
|
|
#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
|
|
#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
|
|
#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
|
|
#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
|
|
#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
|
|
|
|
/* Bit definitions for PMU_SECONDARY_INT2 */
|
|
#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
|
|
#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
|
|
#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
|
|
#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
|
|
#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
|
|
#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
|
|
#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
|
|
#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
|
|
|
|
/* Registers for function RESOURCE */
|
|
#define PALMAS_CLK32KG_CTRL 0x00
|
|
#define PALMAS_CLK32KGAUDIO_CTRL 0x01
|
|
#define PALMAS_REGEN1_CTRL 0x02
|
|
#define PALMAS_REGEN2_CTRL 0x03
|
|
#define PALMAS_SYSEN1_CTRL 0x04
|
|
#define PALMAS_SYSEN2_CTRL 0x05
|
|
#define PALMAS_NSLEEP_RES_ASSIGN 0x06
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
|
|
#define PALMAS_ENABLE1_RES_ASSIGN 0x0A
|
|
#define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
|
|
#define PALMAS_ENABLE2_RES_ASSIGN 0x0E
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
|
|
#define PALMAS_REGEN3_CTRL 0x12
|
|
|
|
/* Bit definitions for CLK32KG_CTRL */
|
|
#define PALMAS_CLK32KG_CTRL_STATUS 0x10
|
|
#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
|
|
#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
|
|
#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
|
|
#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for CLK32KGAUDIO_CTRL */
|
|
#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
|
|
#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
|
|
#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
|
|
#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
|
|
#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
|
|
#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
|
|
#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for REGEN1_CTRL */
|
|
#define PALMAS_REGEN1_CTRL_STATUS 0x10
|
|
#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
|
|
#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
|
|
#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
|
|
#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for REGEN2_CTRL */
|
|
#define PALMAS_REGEN2_CTRL_STATUS 0x10
|
|
#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
|
|
#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
|
|
#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
|
|
#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for SYSEN1_CTRL */
|
|
#define PALMAS_SYSEN1_CTRL_STATUS 0x10
|
|
#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
|
|
#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
|
|
#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
|
|
#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for SYSEN2_CTRL */
|
|
#define PALMAS_SYSEN2_CTRL_STATUS 0x10
|
|
#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
|
|
#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
|
|
#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
|
|
#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for NSLEEP_RES_ASSIGN */
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
|
|
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
|
|
|
|
/* Bit definitions for NSLEEP_SMPS_ASSIGN */
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
|
|
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
|
|
|
|
/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
|
|
|
|
/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
|
|
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
|
|
|
|
/* Bit definitions for ENABLE1_RES_ASSIGN */
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
|
|
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
|
|
|
|
/* Bit definitions for ENABLE1_SMPS_ASSIGN */
|
|
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
|
|
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
|
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#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
|
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#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
|
|
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
|
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#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
|
|
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
|
|
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
|
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#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
|
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#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
|
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#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
|
|
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
|
|
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
|
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#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
|
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#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
|
|
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
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|
|
|
/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
|
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#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
|
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#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
|
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#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
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|
|
/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
|
|
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
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|
|
|
/* Bit definitions for ENABLE2_RES_ASSIGN */
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
|
|
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
|
|
|
|
/* Bit definitions for ENABLE2_SMPS_ASSIGN */
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
|
|
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
|
|
|
|
/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
|
|
|
|
/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
|
|
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
|
|
|
|
/* Bit definitions for REGEN3_CTRL */
|
|
#define PALMAS_REGEN3_CTRL_STATUS 0x10
|
|
#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
|
|
#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
|
|
#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
|
|
#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Registers for function PAD_CONTROL */
|
|
#define PALMAS_OD_OUTPUT_CTRL2 0x02
|
|
#define PALMAS_POLARITY_CTRL2 0x03
|
|
#define PALMAS_PU_PD_INPUT_CTRL1 0x04
|
|
#define PALMAS_PU_PD_INPUT_CTRL2 0x05
|
|
#define PALMAS_PU_PD_INPUT_CTRL3 0x06
|
|
#define PALMAS_PU_PD_INPUT_CTRL5 0x07
|
|
#define PALMAS_OD_OUTPUT_CTRL 0x08
|
|
#define PALMAS_POLARITY_CTRL 0x09
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
|
|
#define PALMAS_I2C_SPI 0x0C
|
|
#define PALMAS_PU_PD_INPUT_CTRL4 0x0D
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
|
|
|
|
/* Bit definitions for PU_PD_INPUT_CTRL1 */
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
|
|
#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
|
|
|
|
/* Bit definitions for PU_PD_INPUT_CTRL2 */
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
|
|
#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
|
|
|
|
/* Bit definitions for PU_PD_INPUT_CTRL3 */
|
|
#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
|
|
#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
|
|
#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
|
|
#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
|
|
#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
|
|
#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
|
|
#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
|
|
#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
|
|
|
|
/* Bit definitions for OD_OUTPUT_CTRL */
|
|
#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
|
|
#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
|
|
#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
|
|
#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
|
|
#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
|
|
#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
|
|
#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
|
|
#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
|
|
|
|
/* Bit definitions for POLARITY_CTRL */
|
|
#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
|
|
#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
|
|
#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
|
|
#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
|
|
#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
|
|
#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
|
|
#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
|
|
#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
|
|
#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
|
|
#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
|
|
#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
|
|
#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
|
|
#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
|
|
#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
|
|
#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
|
|
#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
|
|
|
|
/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
|
|
|
|
/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
|
|
|
|
/* Bit definitions for I2C_SPI */
|
|
#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
|
|
#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
|
|
#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
|
|
#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
|
|
#define PALMAS_I2C_SPI_ID_I2C2 0x20
|
|
#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
|
|
#define PALMAS_I2C_SPI_I2C_SPI 0x10
|
|
#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
|
|
#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
|
|
#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
|
|
|
|
/* Bit definitions for PU_PD_INPUT_CTRL4 */
|
|
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
|
|
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
|
|
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
|
|
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
|
|
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
|
|
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
|
|
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
|
|
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
|
|
|
|
/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
|
|
#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
|
|
|
|
/* Registers for function LED_PWM */
|
|
#define PALMAS_LED_PERIOD_CTRL 0x00
|
|
#define PALMAS_LED_CTRL 0x01
|
|
#define PALMAS_PWM_CTRL1 0x02
|
|
#define PALMAS_PWM_CTRL2 0x03
|
|
|
|
/* Bit definitions for LED_PERIOD_CTRL */
|
|
#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
|
|
#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
|
|
#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
|
|
#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
|
|
|
|
/* Bit definitions for LED_CTRL */
|
|
#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
|
|
#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
|
|
#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
|
|
#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
|
|
#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
|
|
#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
|
|
#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
|
|
#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
|
|
|
|
/* Bit definitions for PWM_CTRL1 */
|
|
#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
|
|
#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
|
|
#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
|
|
#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
|
|
|
|
/* Bit definitions for PWM_CTRL2 */
|
|
#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
|
|
#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
|
|
|
|
/* Registers for function INTERRUPT */
|
|
#define PALMAS_INT1_STATUS 0x00
|
|
#define PALMAS_INT1_MASK 0x01
|
|
#define PALMAS_INT1_LINE_STATE 0x02
|
|
#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
|
|
#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
|
|
#define PALMAS_INT2_STATUS 0x05
|
|
#define PALMAS_INT2_MASK 0x06
|
|
#define PALMAS_INT2_LINE_STATE 0x07
|
|
#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
|
|
#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
|
|
#define PALMAS_INT3_STATUS 0x0A
|
|
#define PALMAS_INT3_MASK 0x0B
|
|
#define PALMAS_INT3_LINE_STATE 0x0C
|
|
#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
|
|
#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
|
|
#define PALMAS_INT4_STATUS 0x0F
|
|
#define PALMAS_INT4_MASK 0x10
|
|
#define PALMAS_INT4_LINE_STATE 0x11
|
|
#define PALMAS_INT4_EDGE_DETECT1 0x12
|
|
#define PALMAS_INT4_EDGE_DETECT2 0x13
|
|
#define PALMAS_INT_CTRL 0x14
|
|
|
|
/* Bit definitions for INT1_STATUS */
|
|
#define PALMAS_INT1_STATUS_VBAT_MON 0x80
|
|
#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
|
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#define PALMAS_INT1_STATUS_VSYS_MON 0x40
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#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
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#define PALMAS_INT1_STATUS_HOTDIE 0x20
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#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
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#define PALMAS_INT1_STATUS_PWRDOWN 0x10
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#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
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#define PALMAS_INT1_STATUS_RPWRON 0x08
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#define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
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#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
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#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
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#define PALMAS_INT1_STATUS_PWRON 0x02
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#define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
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#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
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#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
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/* Bit definitions for INT1_MASK */
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#define PALMAS_INT1_MASK_VBAT_MON 0x80
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#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
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#define PALMAS_INT1_MASK_VSYS_MON 0x40
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#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
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#define PALMAS_INT1_MASK_HOTDIE 0x20
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#define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
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#define PALMAS_INT1_MASK_PWRDOWN 0x10
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#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
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#define PALMAS_INT1_MASK_RPWRON 0x08
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#define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
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#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
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#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
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#define PALMAS_INT1_MASK_PWRON 0x02
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#define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
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#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
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#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
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/* Bit definitions for INT1_LINE_STATE */
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#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
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#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
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#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
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#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
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#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
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#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
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#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
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#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
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#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
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#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
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#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
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#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
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#define PALMAS_INT1_LINE_STATE_PWRON 0x02
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#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
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#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
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#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
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/* Bit definitions for INT2_STATUS */
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#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
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#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
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#define PALMAS_INT2_STATUS_SHORT 0x40
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#define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
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#define PALMAS_INT2_STATUS_FBI_BB 0x20
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#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
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#define PALMAS_INT2_STATUS_RESET_IN 0x10
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#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
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#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
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#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
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#define PALMAS_INT2_STATUS_WDT 0x04
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#define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
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#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
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#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
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#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
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#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
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/* Bit definitions for INT2_MASK */
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#define PALMAS_INT2_MASK_VAC_ACOK 0x80
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#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
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#define PALMAS_INT2_MASK_SHORT 0x40
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#define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
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#define PALMAS_INT2_MASK_FBI_BB 0x20
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#define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
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#define PALMAS_INT2_MASK_RESET_IN 0x10
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#define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
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#define PALMAS_INT2_MASK_BATREMOVAL 0x08
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#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
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#define PALMAS_INT2_MASK_WDT 0x04
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#define PALMAS_INT2_MASK_WDT_SHIFT 0x02
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#define PALMAS_INT2_MASK_RTC_TIMER 0x02
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#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
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#define PALMAS_INT2_MASK_RTC_ALARM 0x01
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#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
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/* Bit definitions for INT2_LINE_STATE */
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#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
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#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
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#define PALMAS_INT2_LINE_STATE_SHORT 0x40
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#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
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#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
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#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
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#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
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#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
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#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
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#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
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#define PALMAS_INT2_LINE_STATE_WDT 0x04
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#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
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#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
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#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
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#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
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#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
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/* Bit definitions for INT3_STATUS */
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#define PALMAS_INT3_STATUS_VBUS 0x80
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#define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
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#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
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#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
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#define PALMAS_INT3_STATUS_ID 0x20
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#define PALMAS_INT3_STATUS_ID_SHIFT 0x05
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#define PALMAS_INT3_STATUS_ID_OTG 0x10
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#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
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#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
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#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
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#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
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#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
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#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
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#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
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#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
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#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
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/* Bit definitions for INT3_MASK */
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#define PALMAS_INT3_MASK_VBUS 0x80
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#define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
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#define PALMAS_INT3_MASK_VBUS_OTG 0x40
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#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
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#define PALMAS_INT3_MASK_ID 0x20
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#define PALMAS_INT3_MASK_ID_SHIFT 0x05
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#define PALMAS_INT3_MASK_ID_OTG 0x10
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#define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
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#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
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#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
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#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
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#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
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#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
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#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
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#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
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#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
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/* Bit definitions for INT3_LINE_STATE */
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#define PALMAS_INT3_LINE_STATE_VBUS 0x80
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#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
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#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
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#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
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#define PALMAS_INT3_LINE_STATE_ID 0x20
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#define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
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#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
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#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
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#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
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#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
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#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
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#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
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#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
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#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
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#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
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#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
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/* Bit definitions for INT4_STATUS */
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#define PALMAS_INT4_STATUS_GPIO_7 0x80
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#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
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#define PALMAS_INT4_STATUS_GPIO_6 0x40
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#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
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#define PALMAS_INT4_STATUS_GPIO_5 0x20
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#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
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#define PALMAS_INT4_STATUS_GPIO_4 0x10
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#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
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#define PALMAS_INT4_STATUS_GPIO_3 0x08
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#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
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#define PALMAS_INT4_STATUS_GPIO_2 0x04
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#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
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#define PALMAS_INT4_STATUS_GPIO_1 0x02
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#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
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#define PALMAS_INT4_STATUS_GPIO_0 0x01
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#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
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/* Bit definitions for INT4_MASK */
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#define PALMAS_INT4_MASK_GPIO_7 0x80
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#define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
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#define PALMAS_INT4_MASK_GPIO_6 0x40
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#define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
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#define PALMAS_INT4_MASK_GPIO_5 0x20
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#define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
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#define PALMAS_INT4_MASK_GPIO_4 0x10
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#define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
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#define PALMAS_INT4_MASK_GPIO_3 0x08
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#define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
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#define PALMAS_INT4_MASK_GPIO_2 0x04
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#define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
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#define PALMAS_INT4_MASK_GPIO_1 0x02
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#define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
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#define PALMAS_INT4_MASK_GPIO_0 0x01
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#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
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/* Bit definitions for INT4_LINE_STATE */
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#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
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#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
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#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
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#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
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#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
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#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
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#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
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#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
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#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
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#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
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#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
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#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
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#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
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#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
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#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
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#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
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/* Bit definitions for INT4_EDGE_DETECT1 */
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
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#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
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/* Bit definitions for INT4_EDGE_DETECT2 */
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
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#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
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/* Bit definitions for INT_CTRL */
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#define PALMAS_INT_CTRL_INT_PENDING 0x04
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#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
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#define PALMAS_INT_CTRL_INT_CLEAR 0x01
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#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
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/* Registers for function USB_OTG */
|
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#define PALMAS_USB_WAKEUP 0x03
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#define PALMAS_USB_VBUS_CTRL_SET 0x04
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#define PALMAS_USB_VBUS_CTRL_CLR 0x05
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#define PALMAS_USB_ID_CTRL_SET 0x06
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#define PALMAS_USB_ID_CTRL_CLEAR 0x07
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#define PALMAS_USB_VBUS_INT_SRC 0x08
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#define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
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#define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
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#define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
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#define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
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#define PALMAS_USB_ID_INT_SRC 0x0F
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#define PALMAS_USB_ID_INT_LATCH_SET 0x10
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#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
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#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
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#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
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#define PALMAS_USB_ID_INT_EN_HI_SET 0x14
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#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
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#define PALMAS_USB_OTG_ADP_CTRL 0x16
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#define PALMAS_USB_OTG_ADP_HIGH 0x17
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#define PALMAS_USB_OTG_ADP_LOW 0x18
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#define PALMAS_USB_OTG_ADP_RISE 0x19
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#define PALMAS_USB_OTG_REVISION 0x1A
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|
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/* Bit definitions for USB_WAKEUP */
|
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#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
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#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
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|
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/* Bit definitions for USB_VBUS_CTRL_SET */
|
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
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#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
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|
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/* Bit definitions for USB_VBUS_CTRL_CLR */
|
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
|
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
|
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
|
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
|
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
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#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
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/* Bit definitions for USB_ID_CTRL_SET */
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#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
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#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
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#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
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#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
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#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
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#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
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#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
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#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
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#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
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#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
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#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
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#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
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/* Bit definitions for USB_ID_CTRL_CLEAR */
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
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#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
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/* Bit definitions for USB_VBUS_INT_SRC */
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#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
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#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
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#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
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#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
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#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
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#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
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#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
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#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
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#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
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#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
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#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
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#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
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#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
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#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
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/* Bit definitions for USB_VBUS_INT_LATCH_SET */
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
|
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
|
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
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#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
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#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
|
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
|
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
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#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
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/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
|
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
|
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
|
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
|
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
|
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
|
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#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
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/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
|
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
|
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
|
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
|
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#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
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/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
|
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
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#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
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/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
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#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
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/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
|
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
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#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
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/* Bit definitions for USB_ID_INT_SRC */
|
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#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
|
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#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
|
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#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
|
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#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
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#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
|
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#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
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#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
|
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#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
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#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
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#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
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|
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/* Bit definitions for USB_ID_INT_LATCH_SET */
|
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#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
|
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#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
|
|
#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
|
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#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
|
|
#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
|
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#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
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#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
|
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#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
|
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#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
|
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#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
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|
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/* Bit definitions for USB_ID_INT_LATCH_CLR */
|
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#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
|
|
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
|
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#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
|
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#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
|
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#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
|
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#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
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#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
|
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#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
|
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#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
|
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#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
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|
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/* Bit definitions for USB_ID_INT_EN_LO_SET */
|
|
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
|
|
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
|
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#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
|
|
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
|
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#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
|
|
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
|
|
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
|
|
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
|
|
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
|
|
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
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|
|
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/* Bit definitions for USB_ID_INT_EN_LO_CLR */
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
|
|
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
|
|
|
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/* Bit definitions for USB_ID_INT_EN_HI_SET */
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
|
|
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
|
|
|
|
/* Bit definitions for USB_ID_INT_EN_HI_CLR */
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
|
|
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
|
|
|
|
/* Bit definitions for USB_OTG_ADP_CTRL */
|
|
#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
|
|
#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
|
|
#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
|
|
#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
|
|
|
|
/* Bit definitions for USB_OTG_ADP_HIGH */
|
|
#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
|
|
#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
|
|
|
|
/* Bit definitions for USB_OTG_ADP_LOW */
|
|
#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
|
|
#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
|
|
|
|
/* Bit definitions for USB_OTG_ADP_RISE */
|
|
#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
|
|
#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
|
|
|
|
/* Bit definitions for USB_OTG_REVISION */
|
|
#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
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#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
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/* Registers for function VIBRATOR */
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#define PALMAS_VIBRA_CTRL 0x00
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/* Bit definitions for VIBRA_CTRL */
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#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
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#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
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#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
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#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
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/* Registers for function GPIO */
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#define PALMAS_GPIO_DATA_IN 0x00
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#define PALMAS_GPIO_DATA_DIR 0x01
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#define PALMAS_GPIO_DATA_OUT 0x02
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#define PALMAS_GPIO_DEBOUNCE_EN 0x03
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#define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
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#define PALMAS_GPIO_SET_DATA_OUT 0x05
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#define PALMAS_PU_PD_GPIO_CTRL1 0x06
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#define PALMAS_PU_PD_GPIO_CTRL2 0x07
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#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
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#define PALMAS_GPIO_DATA_IN2 0x09
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#define PALMAS_GPIO_DATA_DIR2 0x0A
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#define PALMAS_GPIO_DATA_OUT2 0x0B
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#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
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#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
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#define PALMAS_GPIO_SET_DATA_OUT2 0x0E
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#define PALMAS_PU_PD_GPIO_CTRL3 0x0F
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#define PALMAS_PU_PD_GPIO_CTRL4 0x10
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#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
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/* Bit definitions for GPIO_DATA_IN */
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#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
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#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
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#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
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#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
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#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
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#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
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#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
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#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
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#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
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#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
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#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
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#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
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#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
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#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
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#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
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#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
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/* Bit definitions for GPIO_DATA_DIR */
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#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
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#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
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#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
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#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
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#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
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#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
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#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
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#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
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#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
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#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
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#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
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#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
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#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
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#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
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#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
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#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
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/* Bit definitions for GPIO_DATA_OUT */
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#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
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#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
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#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
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#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
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#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
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#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
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#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
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#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
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#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
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#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
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#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
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#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
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#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
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#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
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#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
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#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
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/* Bit definitions for GPIO_DEBOUNCE_EN */
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
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#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
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/* Bit definitions for GPIO_CLEAR_DATA_OUT */
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
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#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
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/* Bit definitions for GPIO_SET_DATA_OUT */
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
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#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
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/* Bit definitions for PU_PD_GPIO_CTRL1 */
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
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#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
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/* Bit definitions for PU_PD_GPIO_CTRL2 */
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
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#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
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/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
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#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
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#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
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#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
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#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
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#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
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#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
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/* Registers for function GPADC */
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#define PALMAS_GPADC_CTRL1 0x00
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#define PALMAS_GPADC_CTRL2 0x01
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#define PALMAS_GPADC_RT_CTRL 0x02
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#define PALMAS_GPADC_AUTO_CTRL 0x03
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#define PALMAS_GPADC_STATUS 0x04
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#define PALMAS_GPADC_RT_SELECT 0x05
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#define PALMAS_GPADC_RT_CONV0_LSB 0x06
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#define PALMAS_GPADC_RT_CONV0_MSB 0x07
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#define PALMAS_GPADC_AUTO_SELECT 0x08
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#define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
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#define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
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#define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
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#define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
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#define PALMAS_GPADC_SW_SELECT 0x0D
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#define PALMAS_GPADC_SW_CONV0_LSB 0x0E
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#define PALMAS_GPADC_SW_CONV0_MSB 0x0F
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#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
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#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
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#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
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#define PALMAS_GPADC_THRES_CONV1_MSB 0x13
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#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
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#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
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/* Bit definitions for GPADC_CTRL1 */
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#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
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#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
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#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
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#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
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#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
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#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
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#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
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#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
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#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
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#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
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/* Bit definitions for GPADC_CTRL2 */
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#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
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#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
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/* Bit definitions for GPADC_RT_CTRL */
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#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
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#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
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#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
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#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
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/* Bit definitions for GPADC_AUTO_CTRL */
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#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
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#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
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#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
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#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
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#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
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#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
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#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
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#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
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#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
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#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
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/* Bit definitions for GPADC_STATUS */
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#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
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#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
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/* Bit definitions for GPADC_RT_SELECT */
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#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
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#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
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#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
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#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
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/* Bit definitions for GPADC_RT_CONV0_LSB */
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#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
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#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
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/* Bit definitions for GPADC_RT_CONV0_MSB */
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#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
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#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
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|
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/* Bit definitions for GPADC_AUTO_SELECT */
|
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#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
|
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#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
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#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
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#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
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|
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/* Bit definitions for GPADC_AUTO_CONV0_LSB */
|
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#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
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#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
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|
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/* Bit definitions for GPADC_AUTO_CONV0_MSB */
|
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#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
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#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
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|
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/* Bit definitions for GPADC_AUTO_CONV1_LSB */
|
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#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
|
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#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
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|
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/* Bit definitions for GPADC_AUTO_CONV1_MSB */
|
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#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
|
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#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
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|
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/* Bit definitions for GPADC_SW_SELECT */
|
|
#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
|
|
#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
|
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#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
|
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#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
|
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#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
|
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#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
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|
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/* Bit definitions for GPADC_SW_CONV0_LSB */
|
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#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
|
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#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
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|
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/* Bit definitions for GPADC_SW_CONV0_MSB */
|
|
#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
|
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#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
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|
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/* Bit definitions for GPADC_THRES_CONV0_LSB */
|
|
#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
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#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
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/* Bit definitions for GPADC_THRES_CONV0_MSB */
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#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
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#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
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#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
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#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
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/* Bit definitions for GPADC_THRES_CONV1_LSB */
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#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
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#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
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/* Bit definitions for GPADC_THRES_CONV1_MSB */
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#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
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#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
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#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
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#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
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/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
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#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
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#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
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#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
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#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
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#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
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#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
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/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
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#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
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#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
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#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
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#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
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/* Registers for function GPADC */
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#define PALMAS_GPADC_TRIM1 0x00
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#define PALMAS_GPADC_TRIM2 0x01
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#define PALMAS_GPADC_TRIM3 0x02
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#define PALMAS_GPADC_TRIM4 0x03
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#define PALMAS_GPADC_TRIM5 0x04
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#define PALMAS_GPADC_TRIM6 0x05
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#define PALMAS_GPADC_TRIM7 0x06
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#define PALMAS_GPADC_TRIM8 0x07
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#define PALMAS_GPADC_TRIM9 0x08
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#define PALMAS_GPADC_TRIM10 0x09
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#define PALMAS_GPADC_TRIM11 0x0A
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#define PALMAS_GPADC_TRIM12 0x0B
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#define PALMAS_GPADC_TRIM13 0x0C
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#define PALMAS_GPADC_TRIM14 0x0D
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#define PALMAS_GPADC_TRIM15 0x0E
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#define PALMAS_GPADC_TRIM16 0x0F
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/* TPS659038 regen2_ctrl offset iss different from palmas */
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#define TPS659038_REGEN2_CTRL 0x12
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/* TPS65917 Interrupt registers */
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/* Registers for function INTERRUPT */
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#define TPS65917_INT1_STATUS 0x00
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#define TPS65917_INT1_MASK 0x01
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#define TPS65917_INT1_LINE_STATE 0x02
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#define TPS65917_INT2_STATUS 0x05
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#define TPS65917_INT2_MASK 0x06
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#define TPS65917_INT2_LINE_STATE 0x07
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#define TPS65917_INT3_STATUS 0x0A
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#define TPS65917_INT3_MASK 0x0B
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#define TPS65917_INT3_LINE_STATE 0x0C
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#define TPS65917_INT4_STATUS 0x0F
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#define TPS65917_INT4_MASK 0x10
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#define TPS65917_INT4_LINE_STATE 0x11
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#define TPS65917_INT4_EDGE_DETECT1 0x12
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#define TPS65917_INT4_EDGE_DETECT2 0x13
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#define TPS65917_INT_CTRL 0x14
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/* Bit definitions for INT1_STATUS */
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#define TPS65917_INT1_STATUS_VSYS_MON 0x40
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#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
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#define TPS65917_INT1_STATUS_HOTDIE 0x20
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#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
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#define TPS65917_INT1_STATUS_PWRDOWN 0x10
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#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
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#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
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#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
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#define TPS65917_INT1_STATUS_PWRON 0x02
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#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
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|
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/* Bit definitions for INT1_MASK */
|
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#define TPS65917_INT1_MASK_VSYS_MON 0x40
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#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
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#define TPS65917_INT1_MASK_HOTDIE 0x20
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#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
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#define TPS65917_INT1_MASK_PWRDOWN 0x10
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#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
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#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
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#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
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#define TPS65917_INT1_MASK_PWRON 0x02
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#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
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|
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/* Bit definitions for INT1_LINE_STATE */
|
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#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
|
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#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
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#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
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#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
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#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
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#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
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#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
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#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
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#define TPS65917_INT1_LINE_STATE_PWRON 0x02
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#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
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|
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/* Bit definitions for INT2_STATUS */
|
|
#define TPS65917_INT2_STATUS_SHORT 0x40
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#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
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#define TPS65917_INT2_STATUS_FSD 0x20
|
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#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
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#define TPS65917_INT2_STATUS_RESET_IN 0x10
|
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#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
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#define TPS65917_INT2_STATUS_WDT 0x04
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#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
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#define TPS65917_INT2_STATUS_OTP_ERROR 0x02
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#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
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|
|
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/* Bit definitions for INT2_MASK */
|
|
#define TPS65917_INT2_MASK_SHORT 0x40
|
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#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
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#define TPS65917_INT2_MASK_FSD 0x20
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#define TPS65917_INT2_MASK_FSD_SHIFT 0x05
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#define TPS65917_INT2_MASK_RESET_IN 0x10
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#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
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#define TPS65917_INT2_MASK_WDT 0x04
|
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#define TPS65917_INT2_MASK_WDT_SHIFT 0x02
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#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
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#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
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|
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/* Bit definitions for INT2_LINE_STATE */
|
|
#define TPS65917_INT2_LINE_STATE_SHORT 0x40
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#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
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#define TPS65917_INT2_LINE_STATE_FSD 0x20
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#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
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#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
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#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
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#define TPS65917_INT2_LINE_STATE_WDT 0x04
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#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
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#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
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#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
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/* Bit definitions for INT3_STATUS */
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|
#define TPS65917_INT3_STATUS_VBUS 0x80
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#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
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#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
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#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
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#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
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#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
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#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
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#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
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/* Bit definitions for INT3_MASK */
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#define TPS65917_INT3_MASK_VBUS 0x80
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#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
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#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
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#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
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#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
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#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
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#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
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#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
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/* Bit definitions for INT3_LINE_STATE */
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#define TPS65917_INT3_LINE_STATE_VBUS 0x80
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#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
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#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
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#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
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#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
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#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
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#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
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#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
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/* Bit definitions for INT4_STATUS */
|
|
#define TPS65917_INT4_STATUS_GPIO_6 0x40
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#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
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#define TPS65917_INT4_STATUS_GPIO_5 0x20
|
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#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
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#define TPS65917_INT4_STATUS_GPIO_4 0x10
|
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#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
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#define TPS65917_INT4_STATUS_GPIO_3 0x08
|
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#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
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#define TPS65917_INT4_STATUS_GPIO_2 0x04
|
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#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
|
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#define TPS65917_INT4_STATUS_GPIO_1 0x02
|
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#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
|
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#define TPS65917_INT4_STATUS_GPIO_0 0x01
|
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#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
|
|
|
|
/* Bit definitions for INT4_MASK */
|
|
#define TPS65917_INT4_MASK_GPIO_6 0x40
|
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#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
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#define TPS65917_INT4_MASK_GPIO_5 0x20
|
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#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
|
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#define TPS65917_INT4_MASK_GPIO_4 0x10
|
|
#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
|
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#define TPS65917_INT4_MASK_GPIO_3 0x08
|
|
#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
|
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#define TPS65917_INT4_MASK_GPIO_2 0x04
|
|
#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
|
|
#define TPS65917_INT4_MASK_GPIO_1 0x02
|
|
#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
|
|
#define TPS65917_INT4_MASK_GPIO_0 0x01
|
|
#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
|
|
|
|
/* Bit definitions for INT4_LINE_STATE */
|
|
#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
|
|
#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
|
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#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
|
|
#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
|
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#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
|
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#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
|
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#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
|
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#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
|
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#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
|
|
#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
|
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#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
|
|
#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
|
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#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
|
|
#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
|
|
|
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/* Bit definitions for INT4_EDGE_DETECT1 */
|
|
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
|
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#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
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|
|
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/* Bit definitions for INT4_EDGE_DETECT2 */
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
|
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#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
|
|
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
|
|
|
|
/* Bit definitions for INT_CTRL */
|
|
#define TPS65917_INT_CTRL_INT_PENDING 0x04
|
|
#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
|
|
#define TPS65917_INT_CTRL_INT_CLEAR 0x01
|
|
#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
|
|
|
|
/* TPS65917 SMPS Registers */
|
|
|
|
/* Registers for function SMPS */
|
|
#define TPS65917_SMPS1_CTRL 0x00
|
|
#define TPS65917_SMPS1_FORCE 0x02
|
|
#define TPS65917_SMPS1_VOLTAGE 0x03
|
|
#define TPS65917_SMPS2_CTRL 0x04
|
|
#define TPS65917_SMPS2_FORCE 0x06
|
|
#define TPS65917_SMPS2_VOLTAGE 0x07
|
|
#define TPS65917_SMPS3_CTRL 0x0C
|
|
#define TPS65917_SMPS3_FORCE 0x0E
|
|
#define TPS65917_SMPS3_VOLTAGE 0x0F
|
|
#define TPS65917_SMPS4_CTRL 0x10
|
|
#define TPS65917_SMPS4_VOLTAGE 0x13
|
|
#define TPS65917_SMPS5_CTRL 0x18
|
|
#define TPS65917_SMPS5_VOLTAGE 0x1B
|
|
#define TPS65917_SMPS_CTRL 0x24
|
|
#define TPS65917_SMPS_PD_CTRL 0x25
|
|
#define TPS65917_SMPS_THERMAL_EN 0x27
|
|
#define TPS65917_SMPS_THERMAL_STATUS 0x28
|
|
#define TPS65917_SMPS_SHORT_STATUS 0x29
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
|
|
#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
|
|
#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
|
|
|
|
/* Bit definitions for SMPS1_CTRL */
|
|
#define TPS65917_SMPS1_CTRL_WR_S 0x80
|
|
#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
|
|
#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
|
|
#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
|
|
#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
|
|
#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
|
|
#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
|
|
#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for SMPS1_FORCE */
|
|
#define TPS65917_SMPS1_FORCE_CMD 0x80
|
|
#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
|
|
#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
|
|
#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
|
|
|
|
/* Bit definitions for SMPS1_VOLTAGE */
|
|
#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
|
|
#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
|
|
#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
|
|
#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
|
|
|
|
/* Bit definitions for SMPS2_CTRL */
|
|
#define TPS65917_SMPS2_CTRL_WR_S 0x80
|
|
#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
|
|
#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
|
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#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
|
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#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
|
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#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
|
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#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
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#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
|
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#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
|
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#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* Bit definitions for SMPS2_FORCE */
|
|
#define TPS65917_SMPS2_FORCE_CMD 0x80
|
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#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
|
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#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
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#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
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|
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/* Bit definitions for SMPS2_VOLTAGE */
|
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#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
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#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
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#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
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#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
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|
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/* Bit definitions for SMPS3_CTRL */
|
|
#define TPS65917_SMPS3_CTRL_WR_S 0x80
|
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#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
|
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#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
|
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#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
|
|
#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
|
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#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
|
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#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
|
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#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
|
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#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
|
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#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
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|
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/* Bit definitions for SMPS3_FORCE */
|
|
#define TPS65917_SMPS3_FORCE_CMD 0x80
|
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#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
|
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#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
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#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
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|
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/* Bit definitions for SMPS3_VOLTAGE */
|
|
#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
|
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#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
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#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
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#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
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|
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/* Bit definitions for SMPS4_CTRL */
|
|
#define TPS65917_SMPS4_CTRL_WR_S 0x80
|
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#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
|
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#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
|
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#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
|
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#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
|
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#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
|
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#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
|
|
#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
|
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#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
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|
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/* Bit definitions for SMPS4_VOLTAGE */
|
|
#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
|
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#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
|
|
#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
|
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#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
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|
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/* Bit definitions for SMPS5_CTRL */
|
|
#define TPS65917_SMPS5_CTRL_WR_S 0x80
|
|
#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
|
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#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
|
|
#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
|
|
#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
|
|
#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
|
|
#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
|
|
#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for SMPS5_VOLTAGE */
|
|
#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
|
|
#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
|
|
#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
|
|
#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
|
|
|
|
/* Bit definitions for SMPS_CTRL */
|
|
#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
|
|
#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
|
|
#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
|
|
#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
|
|
|
|
/* Bit definitions for SMPS_PD_CTRL */
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
|
|
#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
|
|
|
|
/* Bit definitions for SMPS_THERMAL_EN */
|
|
#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
|
|
#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
|
|
#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
|
|
#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
|
|
#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
|
|
#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
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|
|
|
/* Bit definitions for SMPS_THERMAL_STATUS */
|
|
#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
|
|
#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
|
|
#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
|
|
#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
|
|
#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
|
|
#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
|
|
|
|
/* Bit definitions for SMPS_SHORT_STATUS */
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
|
|
#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
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|
|
|
/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
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#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
|
|
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
|
|
|
|
/* Bit definitions for SMPS_POWERGOOD_MASK1 */
|
|
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
|
|
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
|
|
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
|
|
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
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#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
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|
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
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|
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
|
|
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
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|
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
|
|
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
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|
|
|
/* Bit definitions for SMPS_POWERGOOD_MASK2 */
|
|
#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
|
|
#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
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#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
|
|
#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
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|
|
|
/* Bit definitions for SMPS_PLL_CTRL */
|
|
|
|
#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
|
|
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
|
|
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
|
|
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
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|
|
/* Registers for function LDO */
|
|
#define TPS65917_LDO1_CTRL 0x00
|
|
#define TPS65917_LDO1_VOLTAGE 0x01
|
|
#define TPS65917_LDO2_CTRL 0x02
|
|
#define TPS65917_LDO2_VOLTAGE 0x03
|
|
#define TPS65917_LDO3_CTRL 0x04
|
|
#define TPS65917_LDO3_VOLTAGE 0x05
|
|
#define TPS65917_LDO4_CTRL 0x0E
|
|
#define TPS65917_LDO4_VOLTAGE 0x0F
|
|
#define TPS65917_LDO5_CTRL 0x12
|
|
#define TPS65917_LDO5_VOLTAGE 0x13
|
|
#define TPS65917_LDO_PD_CTRL1 0x1B
|
|
#define TPS65917_LDO_PD_CTRL2 0x1C
|
|
#define TPS65917_LDO_SHORT_STATUS1 0x1D
|
|
#define TPS65917_LDO_SHORT_STATUS2 0x1E
|
|
#define TPS65917_LDO_PD_CTRL3 0x2D
|
|
#define TPS65917_LDO_SHORT_STATUS3 0x2E
|
|
|
|
/* Bit definitions for LDO1_CTRL */
|
|
#define TPS65917_LDO1_CTRL_WR_S 0x80
|
|
#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
|
|
#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
|
|
#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
|
|
#define TPS65917_LDO1_CTRL_STATUS 0x10
|
|
#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
|
|
#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
|
|
#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO1_VOLTAGE */
|
|
#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
|
|
#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO2_CTRL */
|
|
#define TPS65917_LDO2_CTRL_WR_S 0x80
|
|
#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
|
|
#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
|
|
#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
|
|
#define TPS65917_LDO2_CTRL_STATUS 0x10
|
|
#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
|
|
#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
|
|
#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO2_VOLTAGE */
|
|
#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
|
|
#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO3_CTRL */
|
|
#define TPS65917_LDO3_CTRL_WR_S 0x80
|
|
#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
|
|
#define TPS65917_LDO3_CTRL_STATUS 0x10
|
|
#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
|
|
#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
|
|
#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO3_VOLTAGE */
|
|
#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
|
|
#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO4_CTRL */
|
|
#define TPS65917_LDO4_CTRL_WR_S 0x80
|
|
#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
|
|
#define TPS65917_LDO4_CTRL_STATUS 0x10
|
|
#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
|
|
#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
|
|
#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO4_VOLTAGE */
|
|
#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
|
|
#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO5_CTRL */
|
|
#define TPS65917_LDO5_CTRL_WR_S 0x80
|
|
#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
|
|
#define TPS65917_LDO5_CTRL_STATUS 0x10
|
|
#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
|
|
#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
|
|
#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO5_VOLTAGE */
|
|
#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
|
|
#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO_PD_CTRL1 */
|
|
#define TPS65917_LDO_PD_CTRL1_LDO4 0x80
|
|
#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
|
|
#define TPS65917_LDO_PD_CTRL1_LDO2 0x02
|
|
#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
|
|
#define TPS65917_LDO_PD_CTRL1_LDO1 0x01
|
|
#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO_PD_CTRL2 */
|
|
#define TPS65917_LDO_PD_CTRL2_LDO3 0x04
|
|
#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
|
|
#define TPS65917_LDO_PD_CTRL2_LDO5 0x02
|
|
#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
|
|
|
|
/* Bit definitions for LDO_PD_CTRL3 */
|
|
#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
|
|
#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
|
|
|
|
/* Bit definitions for LDO_SHORT_STATUS1 */
|
|
#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
|
|
#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
|
|
#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
|
|
#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
|
|
#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
|
|
#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
|
|
|
|
/* Bit definitions for LDO_SHORT_STATUS2 */
|
|
#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
|
|
#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
|
|
#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
|
|
#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
|
|
|
|
/* Bit definitions for LDO_SHORT_STATUS2 */
|
|
#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
|
|
#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
|
|
|
|
/* Bit definitions for REGEN1_CTRL */
|
|
#define TPS65917_REGEN1_CTRL_STATUS 0x10
|
|
#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
|
|
#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
|
|
#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for PLLEN_CTRL */
|
|
#define TPS65917_PLLEN_CTRL_STATUS 0x10
|
|
#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
|
|
#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
|
|
#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for REGEN2_CTRL */
|
|
#define TPS65917_REGEN2_CTRL_STATUS 0x10
|
|
#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
|
|
#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
|
|
#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
|
|
#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
|
|
#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
|
|
|
|
/* Bit definitions for NSLEEP_RES_ASSIGN */
|
|
#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
|
|
#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
|
|
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
|
|
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
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#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
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#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
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#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
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#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
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/* Bit definitions for NSLEEP_SMPS_ASSIGN */
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
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#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
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/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
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#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
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#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
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#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
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#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
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#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
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#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
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/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
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#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
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#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
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#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
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#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
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/* Bit definitions for ENABLE1_RES_ASSIGN */
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#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
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#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
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#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
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#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
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#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
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#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
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#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
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#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
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/* Bit definitions for ENABLE1_SMPS_ASSIGN */
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
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#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
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/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
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#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
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#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
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#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
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#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
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#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
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#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
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/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
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#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
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#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
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#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
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#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
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/* Bit definitions for ENABLE2_RES_ASSIGN */
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#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
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#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
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#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
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#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
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#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
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#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
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#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
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#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
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/* Bit definitions for ENABLE2_SMPS_ASSIGN */
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
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#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
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/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
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#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
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#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
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#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
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#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
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#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
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#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
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/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
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#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
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#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
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#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
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#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
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/* Bit definitions for REGEN3_CTRL */
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#define TPS65917_REGEN3_CTRL_STATUS 0x10
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#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
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#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
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#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
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#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
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#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
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/* POWERHOLD Mask field for PRIMARY_SECONDARY_PAD2 register */
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#define TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0xC
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/* Registers for function RESOURCE */
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#define TPS65917_REGEN1_CTRL 0x2
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#define TPS65917_PLLEN_CTRL 0x3
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#define TPS65917_NSLEEP_RES_ASSIGN 0x6
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#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
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#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
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#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
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#define TPS65917_ENABLE1_RES_ASSIGN 0xA
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#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
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#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
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#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
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#define TPS65917_ENABLE2_RES_ASSIGN 0xE
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#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
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#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
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#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
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#define TPS65917_REGEN2_CTRL 0x12
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#define TPS65917_REGEN3_CTRL 0x13
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static inline int palmas_read(struct palmas *palmas, unsigned int base,
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unsigned int reg, unsigned int *val)
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{
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unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
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int slave_id = PALMAS_BASE_TO_SLAVE(base);
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return regmap_read(palmas->regmap[slave_id], addr, val);
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}
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static inline int palmas_write(struct palmas *palmas, unsigned int base,
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unsigned int reg, unsigned int value)
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{
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unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
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int slave_id = PALMAS_BASE_TO_SLAVE(base);
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return regmap_write(palmas->regmap[slave_id], addr, value);
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}
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static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
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unsigned int reg, const void *val, size_t val_count)
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{
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unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
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int slave_id = PALMAS_BASE_TO_SLAVE(base);
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return regmap_bulk_write(palmas->regmap[slave_id], addr,
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val, val_count);
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}
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static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
|
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unsigned int reg, void *val, size_t val_count)
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{
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unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
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int slave_id = PALMAS_BASE_TO_SLAVE(base);
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return regmap_bulk_read(palmas->regmap[slave_id], addr,
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val, val_count);
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}
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static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
|
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unsigned int reg, unsigned int mask, unsigned int val)
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|
{
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unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
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int slave_id = PALMAS_BASE_TO_SLAVE(base);
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return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
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}
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static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
|
|
{
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return regmap_irq_get_virq(palmas->irq_data, irq);
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}
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int palmas_ext_control_req_config(struct palmas *palmas,
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|
enum palmas_external_requestor_id ext_control_req_id,
|
|
int ext_ctrl, bool enable);
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#endif /* __LINUX_MFD_PALMAS_H */
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