299b610117
SGI Octane (IP30) doesn't have RTC register directly mapped into CPU address space, but accesses RTC registers with an address and data register. This is now supported by additional access functions, which are selected by a new field in platform data. Removed plat_read/plat_write since there is no user and their usage could introduce lifetime issue, when functions are placed in different modules. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Acked-by: Joshua Kinard <kumba@gentoo.org> Reviewed-by: Joshua Kinard <kumba@gentoo.org> Link: https://lore.kernel.org/r/20191014214621.25257-1-tbogendoerfer@suse.de Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
369 lines
14 KiB
C
369 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Definitions for the registers, addresses, and platform data of the
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* DS1685/DS1687-series RTC chips.
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*
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* This Driver also works for the DS17X85/DS17X87 RTC chips. Functionally
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* similar to the DS1685/DS1687, they support a few extra features which
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* include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
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* write counter.
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*
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* Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
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* Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
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*
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* References:
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* DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
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* DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
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* DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
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* Application Note 90, Using the Multiplex Bus RTC Extended Features.
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*/
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#ifndef _LINUX_RTC_DS1685_H_
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#define _LINUX_RTC_DS1685_H_
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#include <linux/rtc.h>
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#include <linux/platform_device.h>
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#include <linux/workqueue.h>
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/**
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* struct ds1685_priv - DS1685 private data structure.
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* @dev: pointer to the rtc_device structure.
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* @regs: iomapped base address pointer of the RTC registers.
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* @regstep: padding/step size between registers (optional).
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* @baseaddr: base address of the RTC device.
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* @size: resource size.
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* @lock: private lock variable for spin locking/unlocking.
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* @work: private workqueue.
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* @irq: IRQ number assigned to the RTC device.
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* @prepare_poweroff: pointer to platform pre-poweroff function.
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* @wake_alarm: pointer to platform wake alarm function.
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* @post_ram_clear: pointer to platform post ram-clear function.
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*/
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struct ds1685_priv {
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struct rtc_device *dev;
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void __iomem *regs;
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void __iomem *data;
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u32 regstep;
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int irq_num;
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bool bcd_mode;
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bool no_irq;
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u8 (*read)(struct ds1685_priv *, int);
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void (*write)(struct ds1685_priv *, int, u8);
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void (*prepare_poweroff)(void);
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void (*wake_alarm)(void);
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void (*post_ram_clear)(void);
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};
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/**
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* struct ds1685_rtc_platform_data - platform data structure.
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* @plat_prepare_poweroff: platform-specific pre-poweroff function.
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* @plat_wake_alarm: platform-specific wake alarm function.
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* @plat_post_ram_clear: platform-specific post ram-clear function.
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*
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* If your platform needs to use a custom padding/step size between
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* registers, or uses one or more of the extended interrupts and needs special
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* handling, then include this header file in your platform definition and
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* set regstep and the plat_* pointers as appropriate.
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*/
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struct ds1685_rtc_platform_data {
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const u32 regstep;
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const bool bcd_mode;
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const bool no_irq;
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const bool uie_unsupported;
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void (*plat_prepare_poweroff)(void);
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void (*plat_wake_alarm)(void);
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void (*plat_post_ram_clear)(void);
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enum {
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ds1685_reg_direct,
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ds1685_reg_indirect
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} access_type;
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};
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/*
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* Time Registers.
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*/
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#define RTC_SECS 0x00 /* Seconds 00-59 */
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#define RTC_SECS_ALARM 0x01 /* Alarm Seconds 00-59 */
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#define RTC_MINS 0x02 /* Minutes 00-59 */
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#define RTC_MINS_ALARM 0x03 /* Alarm Minutes 00-59 */
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#define RTC_HRS 0x04 /* Hours 01-12 AM/PM || 00-23 */
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#define RTC_HRS_ALARM 0x05 /* Alarm Hours 01-12 AM/PM || 00-23 */
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#define RTC_WDAY 0x06 /* Day of Week 01-07 */
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#define RTC_MDAY 0x07 /* Day of Month 01-31 */
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#define RTC_MONTH 0x08 /* Month 01-12 */
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#define RTC_YEAR 0x09 /* Year 00-99 */
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#define RTC_CENTURY 0x48 /* Century 00-99 */
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#define RTC_MDAY_ALARM 0x49 /* Alarm Day of Month 01-31 */
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/*
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* Bit masks for the Time registers in BCD Mode (DM = 0).
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*/
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#define RTC_SECS_BCD_MASK 0x7f /* - x x x x x x x */
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#define RTC_MINS_BCD_MASK 0x7f /* - x x x x x x x */
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#define RTC_HRS_12_BCD_MASK 0x1f /* - - - x x x x x */
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#define RTC_HRS_24_BCD_MASK 0x3f /* - - x x x x x x */
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#define RTC_MDAY_BCD_MASK 0x3f /* - - x x x x x x */
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#define RTC_MONTH_BCD_MASK 0x1f /* - - - x x x x x */
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#define RTC_YEAR_BCD_MASK 0xff /* x x x x x x x x */
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/*
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* Bit masks for the Time registers in BIN Mode (DM = 1).
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*/
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#define RTC_SECS_BIN_MASK 0x3f /* - - x x x x x x */
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#define RTC_MINS_BIN_MASK 0x3f /* - - x x x x x x */
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#define RTC_HRS_12_BIN_MASK 0x0f /* - - - - x x x x */
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#define RTC_HRS_24_BIN_MASK 0x1f /* - - - x x x x x */
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#define RTC_MDAY_BIN_MASK 0x1f /* - - - x x x x x */
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#define RTC_MONTH_BIN_MASK 0x0f /* - - - - x x x x */
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#define RTC_YEAR_BIN_MASK 0x7f /* - x x x x x x x */
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/*
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* Bit masks common for the Time registers in BCD or BIN Mode.
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*/
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#define RTC_WDAY_MASK 0x07 /* - - - - - x x x */
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#define RTC_CENTURY_MASK 0xff /* x x x x x x x x */
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#define RTC_MDAY_ALARM_MASK 0xff /* x x x x x x x x */
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#define RTC_HRS_AMPM_MASK BIT(7) /* Mask for the AM/PM bit */
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/*
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* Control Registers.
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*/
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#define RTC_CTRL_A 0x0a /* Control Register A */
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#define RTC_CTRL_B 0x0b /* Control Register B */
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#define RTC_CTRL_C 0x0c /* Control Register C */
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#define RTC_CTRL_D 0x0d /* Control Register D */
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#define RTC_EXT_CTRL_4A 0x4a /* Extended Control Register 4A */
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#define RTC_EXT_CTRL_4B 0x4b /* Extended Control Register 4B */
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/*
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* Bit names in Control Register A.
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*/
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#define RTC_CTRL_A_UIP BIT(7) /* Update In Progress */
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#define RTC_CTRL_A_DV2 BIT(6) /* Countdown Chain */
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#define RTC_CTRL_A_DV1 BIT(5) /* Oscillator Enable */
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#define RTC_CTRL_A_DV0 BIT(4) /* Bank Select */
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#define RTC_CTRL_A_RS2 BIT(2) /* Rate-Selection Bit 2 */
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#define RTC_CTRL_A_RS3 BIT(3) /* Rate-Selection Bit 3 */
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#define RTC_CTRL_A_RS1 BIT(1) /* Rate-Selection Bit 1 */
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#define RTC_CTRL_A_RS0 BIT(0) /* Rate-Selection Bit 0 */
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#define RTC_CTRL_A_RS_MASK 0x0f /* RS3 + RS2 + RS1 + RS0 */
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/*
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* Bit names in Control Register B.
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*/
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#define RTC_CTRL_B_SET BIT(7) /* SET Bit */
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#define RTC_CTRL_B_PIE BIT(6) /* Periodic-Interrupt Enable */
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#define RTC_CTRL_B_AIE BIT(5) /* Alarm-Interrupt Enable */
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#define RTC_CTRL_B_UIE BIT(4) /* Update-Ended Interrupt-Enable */
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#define RTC_CTRL_B_SQWE BIT(3) /* Square-Wave Enable */
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#define RTC_CTRL_B_DM BIT(2) /* Data Mode */
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#define RTC_CTRL_B_2412 BIT(1) /* 12-Hr/24-Hr Mode */
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#define RTC_CTRL_B_DSE BIT(0) /* Daylight Savings Enable */
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#define RTC_CTRL_B_PAU_MASK 0x70 /* PIE + AIE + UIE */
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/*
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* Bit names in Control Register C.
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*
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* BIT(0), BIT(1), BIT(2), & BIT(3) are unused, always return 0, and cannot
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* be written to.
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*/
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#define RTC_CTRL_C_IRQF BIT(7) /* Interrupt-Request Flag */
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#define RTC_CTRL_C_PF BIT(6) /* Periodic-Interrupt Flag */
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#define RTC_CTRL_C_AF BIT(5) /* Alarm-Interrupt Flag */
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#define RTC_CTRL_C_UF BIT(4) /* Update-Ended Interrupt Flag */
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#define RTC_CTRL_C_PAU_MASK 0x70 /* PF + AF + UF */
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/*
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* Bit names in Control Register D.
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*
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* BIT(0) through BIT(6) are unused, always return 0, and cannot
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* be written to.
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*/
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#define RTC_CTRL_D_VRT BIT(7) /* Valid RAM and Time */
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/*
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* Bit names in Extended Control Register 4A.
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*
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* On the DS1685/DS1687/DS1689/DS1693, BIT(4) and BIT(5) are reserved for
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* future use. They can be read from and written to, but have no effect
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* on the RTC's operation.
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*
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* On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows
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* access to the extended NV-SRAM by automatically incrementing the address
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* register when they are read from or written to.
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*/
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#define RTC_CTRL_4A_VRT2 BIT(7) /* Auxillary Battery Status */
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#define RTC_CTRL_4A_INCR BIT(6) /* Increment-in-Progress Status */
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#define RTC_CTRL_4A_PAB BIT(3) /* Power-Active Bar Control */
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#define RTC_CTRL_4A_RF BIT(2) /* RAM-Clear Flag */
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#define RTC_CTRL_4A_WF BIT(1) /* Wake-Up Alarm Flag */
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#define RTC_CTRL_4A_KF BIT(0) /* Kickstart Flag */
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#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
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#define RTC_CTRL_4A_BME BIT(5) /* Burst-Mode Enable */
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#endif
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#define RTC_CTRL_4A_RWK_MASK 0x07 /* RF + WF + KF */
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/*
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* Bit names in Extended Control Register 4B.
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*/
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#define RTC_CTRL_4B_ABE BIT(7) /* Auxillary Battery Enable */
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#define RTC_CTRL_4B_E32K BIT(6) /* Enable 32.768Hz on SQW Pin */
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#define RTC_CTRL_4B_CS BIT(5) /* Crystal Select */
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#define RTC_CTRL_4B_RCE BIT(4) /* RAM Clear-Enable */
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#define RTC_CTRL_4B_PRS BIT(3) /* PAB Reset-Select */
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#define RTC_CTRL_4B_RIE BIT(2) /* RAM Clear-Interrupt Enable */
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#define RTC_CTRL_4B_WIE BIT(1) /* Wake-Up Alarm-Interrupt Enable */
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#define RTC_CTRL_4B_KSE BIT(0) /* Kickstart Interrupt-Enable */
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#define RTC_CTRL_4B_RWK_MASK 0x07 /* RIE + WIE + KSE */
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/*
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* Misc register names in Bank 1.
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*
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* The DV0 bit in Control Register A must be set to 1 for these registers
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* to become available, including Extended Control Registers 4A & 4B.
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*/
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#define RTC_BANK1_SSN_MODEL 0x40 /* Model Number */
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#define RTC_BANK1_SSN_BYTE_1 0x41 /* 1st Byte of Serial Number */
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#define RTC_BANK1_SSN_BYTE_2 0x42 /* 2nd Byte of Serial Number */
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#define RTC_BANK1_SSN_BYTE_3 0x43 /* 3rd Byte of Serial Number */
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#define RTC_BANK1_SSN_BYTE_4 0x44 /* 4th Byte of Serial Number */
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#define RTC_BANK1_SSN_BYTE_5 0x45 /* 5th Byte of Serial Number */
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#define RTC_BANK1_SSN_BYTE_6 0x46 /* 6th Byte of Serial Number */
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#define RTC_BANK1_SSN_CRC 0x47 /* Serial CRC Byte */
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#define RTC_BANK1_RAM_DATA_PORT 0x53 /* Extended RAM Data Port */
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/*
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* Model-specific registers in Bank 1.
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*
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* The addresses below differ depending on the model of the RTC chip
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* selected in the kernel configuration. Not all of these features are
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* supported in the main driver at present.
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*
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* DS1685/DS1687 - Extended NV-SRAM address (LSB only).
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* DS1689/DS1693 - Vcc, Vbat, Pwr Cycle Counters & Customer-specific S/N.
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* DS17x85/DS17x87 - Extended NV-SRAM addresses (MSB & LSB) & Write counter.
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*/
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#if defined(CONFIG_RTC_DRV_DS1685)
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#define RTC_BANK1_RAM_ADDR 0x50 /* NV-SRAM Addr */
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#elif defined(CONFIG_RTC_DRV_DS1689)
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#define RTC_BANK1_VCC_CTR_LSB 0x54 /* Vcc Counter Addr (LSB) */
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#define RTC_BANK1_VCC_CTR_MSB 0x57 /* Vcc Counter Addr (MSB) */
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#define RTC_BANK1_VBAT_CTR_LSB 0x58 /* Vbat Counter Addr (LSB) */
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#define RTC_BANK1_VBAT_CTR_MSB 0x5b /* Vbat Counter Addr (MSB) */
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#define RTC_BANK1_PWR_CTR_LSB 0x5c /* Pwr Cycle Counter Addr (LSB) */
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#define RTC_BANK1_PWR_CTR_MSB 0x5d /* Pwr Cycle Counter Addr (MSB) */
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#define RTC_BANK1_UNIQ_SN 0x60 /* Customer-specific S/N */
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#else /* DS17x85/DS17x87 */
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#define RTC_BANK1_RAM_ADDR_LSB 0x50 /* NV-SRAM Addr (LSB) */
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#define RTC_BANK1_RAM_ADDR_MSB 0x51 /* NV-SRAM Addr (MSB) */
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#define RTC_BANK1_WRITE_CTR 0x5e /* RTC Write Counter */
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#endif
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/*
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* Model numbers.
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*
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* The DS1688/DS1691 and DS1689/DS1693 chips share the same model number
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* and the manual doesn't indicate any major differences. As such, they
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* are regarded as the same chip in this driver.
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*/
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#define RTC_MODEL_DS1685 0x71 /* DS1685/DS1687 */
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#define RTC_MODEL_DS17285 0x72 /* DS17285/DS17287 */
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#define RTC_MODEL_DS1689 0x73 /* DS1688/DS1691/DS1689/DS1693 */
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#define RTC_MODEL_DS17485 0x74 /* DS17485/DS17487 */
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#define RTC_MODEL_DS17885 0x78 /* DS17885/DS17887 */
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/*
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* Periodic Interrupt Rates / Square-Wave Output Frequency
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*
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* Periodic rates are selected by setting the RS3-RS0 bits in Control
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* Register A and enabled via either the E32K bit in Extended Control
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* Register 4B or the SQWE bit in Control Register B.
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*
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* E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz
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* on the SQW pin of the RTC chip. While there are 16 possible selections,
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* the 1-of-16 decoder is only able to divide the base 32768Hz signal into 13
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* smaller frequencies. The values 0x01 and 0x02 are not used and are
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* synonymous with 0x08 and 0x09, respectively.
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*
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* When E32K is set to a logic 1, periodic interrupts are disabled and reading
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* /dev/rtc will return -EINVAL. This also applies if the periodic interrupt
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* frequency is set to 0Hz.
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*
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* Not currently used by the rtc-ds1685 driver because the RTC core removed
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* support for hardware-generated periodic-interrupts in favour of
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* hrtimer-generated interrupts. But these defines are kept around for use
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* in userland, as documentation to the hardware, and possible future use if
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* hardware-generated periodic interrupts are ever added back.
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*/
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/* E32K RS3 RS2 RS1 RS0 */
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#define RTC_SQW_8192HZ 0x03 /* 0 0 0 1 1 */
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#define RTC_SQW_4096HZ 0x04 /* 0 0 1 0 0 */
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#define RTC_SQW_2048HZ 0x05 /* 0 0 1 0 1 */
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#define RTC_SQW_1024HZ 0x06 /* 0 0 1 1 0 */
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#define RTC_SQW_512HZ 0x07 /* 0 0 1 1 1 */
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#define RTC_SQW_256HZ 0x08 /* 0 1 0 0 0 */
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#define RTC_SQW_128HZ 0x09 /* 0 1 0 0 1 */
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#define RTC_SQW_64HZ 0x0a /* 0 1 0 1 0 */
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#define RTC_SQW_32HZ 0x0b /* 0 1 0 1 1 */
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#define RTC_SQW_16HZ 0x0c /* 0 1 1 0 0 */
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#define RTC_SQW_8HZ 0x0d /* 0 1 1 0 1 */
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#define RTC_SQW_4HZ 0x0e /* 0 1 1 1 0 */
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#define RTC_SQW_2HZ 0x0f /* 0 1 1 1 1 */
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#define RTC_SQW_0HZ 0x00 /* 0 0 0 0 0 */
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#define RTC_SQW_32768HZ 32768 /* 1 - - - - */
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#define RTC_MAX_USER_FREQ 8192
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/*
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* NVRAM data & addresses:
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* - 50 bytes of NVRAM are available just past the clock registers.
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* - 64 additional bytes are available in Bank0.
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*
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* Extended, battery-backed NV-SRAM:
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* - DS1685/DS1687 - 128 bytes.
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* - DS1689/DS1693 - 0 bytes.
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* - DS17285/DS17287 - 2048 bytes.
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* - DS17485/DS17487 - 4096 bytes.
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* - DS17885/DS17887 - 8192 bytes.
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*/
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#define NVRAM_TIME_BASE 0x0e /* NVRAM Addr in Time regs */
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#define NVRAM_BANK0_BASE 0x40 /* NVRAM Addr in Bank0 regs */
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#define NVRAM_SZ_TIME 50
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#define NVRAM_SZ_BANK0 64
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#if defined(CONFIG_RTC_DRV_DS1685)
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# define NVRAM_SZ_EXTND 128
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#elif defined(CONFIG_RTC_DRV_DS1689)
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# define NVRAM_SZ_EXTND 0
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#elif defined(CONFIG_RTC_DRV_DS17285)
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# define NVRAM_SZ_EXTND 2048
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#elif defined(CONFIG_RTC_DRV_DS17485)
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# define NVRAM_SZ_EXTND 4096
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#elif defined(CONFIG_RTC_DRV_DS17885)
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# define NVRAM_SZ_EXTND 8192
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#endif
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#define NVRAM_TOTAL_SZ_BANK0 (NVRAM_SZ_TIME + NVRAM_SZ_BANK0)
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#define NVRAM_TOTAL_SZ (NVRAM_TOTAL_SZ_BANK0 + NVRAM_SZ_EXTND)
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/*
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* Function Prototypes.
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*/
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extern void __noreturn
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ds1685_rtc_poweroff(struct platform_device *pdev);
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#endif /* _LINUX_RTC_DS1685_H_ */
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