93 lines
2.7 KiB
Plaintext
93 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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cm40_subsys: bus@34000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x34000000 0x0 0x34000000 0x4000000>;
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cm40_ipg_clk: clock-cm40-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <132000000>;
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clock-output-names = "cm40_ipg_clk";
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};
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cm40_i2c: i2c@37230000 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x37230000 0x1000>;
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interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&cm40_intmux>;
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clocks = <&cm40_i2c_lpcg 0>,
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<&cm40_i2c_lpcg 1>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_M4_0_I2C>;
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status = "disabled";
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};
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cm40_i2c_lpcg: clock-controller@37630000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x37630000 0x1000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
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<&cm40_ipg_clk>;
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bit-offset = <0 16>;
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clock-output-names = "cm40_lpcg_i2c_clk",
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"cm40_lpcg_i2c_ipg_clk";
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power-domains = <&pd IMX_SC_R_M4_0_I2C>;
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};
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cm40_intmux: intmux@37400000 {
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compatible = "nxp,imx8qxp-intmux", "nxp,imx-intmux";
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reg = <0x37400000 0x1000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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clocks = <&cm40_ipg_clk>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
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status = "disabled";
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};
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cm40_lpuart: serial@37220000 {
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compatible = "fsl,imx8qxp-lpuart";
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reg = <0x37220000 0x1000>;
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interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&cm40_intmux>;
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clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>;
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clock-names = "ipg", "baud";
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assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_M4_0_UART>;
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status = "disabled";
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};
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cm40_uart_lpcg: clock-controller@37620000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x37620000 0x1000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
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<&cm40_ipg_clk>;
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bit-offset = <0 4>;
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clock-output-names = "cm40_lpcg_uart_clk",
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"cm40_lpcg_uart_ipg_clk";
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power-domains = <&pd IMX_SC_R_M4_0_UART>;
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};
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};
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