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alistair23-linux/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-val.dts

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019~2020 NXP
*/
/dts-v1/;
#include "imx8dxl.dtsi"
/ {
model = "Freescale i.MX8DXL DDR3 EVK";
compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl";
chosen {
stdout-path = &lpuart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x20000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
* Shouldn't be used at A core and Linux side.
*
*/
m4_reserved: m4@0x88000000 {
no-map;
reg = <0 0x88000000 0 0x8000000>;
};
rpmsg_reserved: rpmsg@0x90000000 {
no-map;
reg = <0 0x90000000 0 0x400000>;
};
rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
compatible = "shared-dma-pool";
no-map;
reg = <0 0x90400000 0 0x100000>;
};
/*
* Memory reserved for optee usage. Please do not use.
* This will be automaticky added to dtb if OP-TEE is installed.
* optee@96000000 {
* reg = <0 0x96000000 0 0x2000000>;
* no-map;
* };
*/
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x8000000>;
alloc-ranges = <0 0x98000000 0 0x8000000>;
linux,cma-default;
};
};
reg_can0_stby: regulator-can0-stby {
compatible = "regulator-fixed";
regulator-name = "can0-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
regulator-name = "can1-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <3480>;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc>;
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
mt35xu512aba0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <133000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&lpspi3 {
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <30000000>;
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pca6416_1: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
pca6416_2: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
pca9548_1: pca9548@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
};
};
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
pca6416_3: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&lsio_gpio2>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
};
pca9548_2: pca9548@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
};
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-1 = <&pinctrl_lpuart1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can0_stby>;
status = "okay";
};
&flexcan3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan3>;
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&lsio_gpio4 {
status = "okay";
};
&lsio_gpio5 {
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay";
nand-on-flash-bbt;
max-cs = <1>;
};
&pcieb{
compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>;
clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
ext_osc = <1>;
status = "disabled";
};
&asrc0 {
fsl,asrc-rate = <48000>;
status = "okay";
};
&thermal_zones {
pmic-thermal0 {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens 497>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device =
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
max-frequency = <100000000>;
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
snps,reset-delays-us = <10 20 200000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
eee-broken-1000t;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-txid";
phy-handle = <&ethphy1>;
fsl,magic-packet;
fsl,rgmii_rxc_dly;
phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <150>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&usbphy1 {
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
disable-over-current;
status = "okay";
};
&usbphy2 {
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
srp-disable;
hnp-disable;
adp-disable;
power-active-high;
disable-over-current;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c
IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c
>;
};
pinctrl_usbotg1: otg1 {
fsl,pins = <
IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
>;
};
pinctrl_usbotg2: otg2 {
fsl,pins = <
IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
>;
};
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c
IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c
IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c
IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c
IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c
IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c
IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c
IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c
IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c
IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c
IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c
IMX8DXL_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c
IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c
IMX8DXL_USDHC1_WP_CONN_NAND_ALE 0x0e00004c
IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x600004c
IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x600004c
IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x600004c
IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x600004c
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8DXL_UART0_RX_ADMA_UART0_RX 0x0600004c
IMX8DXL_UART0_TX_ADMA_UART0_TX 0x0600004c
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
IMX8DXL_UART1_TX_ADMA_UART1_TX 0x0600004c
IMX8DXL_UART1_RX_ADMA_UART1_RX 0x0600004c
IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x0600004c
IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x0600004c
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021
IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021
>;
};
pinctrl_flexcan3: flexcan3grp {
fsl,pins = <
IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021
IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040
IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040
IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000040
IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040
IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040
IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040
IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040
IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_pcieb: pcieagrp{
fsl,pins = <
IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021
IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021
IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021
>;
};
pinctrl_adc: adcgrp{
fsl,pins = <
IMX8DXL_ADC_IN0_ADMA_ADC_IN0 0x06000021
IMX8DXL_ADC_IN1_ADMA_ADC_IN1 0x06000021
IMX8DXL_ADC_IN4_ADMA_ADC_IN4 0x06000021
IMX8DXL_ADC_IN5_ADMA_ADC_IN5 0x06000021
>;
};
};
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