61 lines
1.2 KiB
Plaintext
61 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017~2019 NXP
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*/
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#include "imx8qm-lpddr4-val.dts"
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&iomuxc {
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pinctrl_lpspi0: lpspi0grp {
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fsl,pins = <
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IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x600004c
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IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x600004c
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IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x600004c
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>;
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};
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pinctrl_lpspi0_cs: lpspi0cs {
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fsl,pins = <
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IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x21
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>;
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};
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pinctrl_lpspi3: lpspi3grp {
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fsl,pins = <
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IMX8QM_SPI3_SCK_DMA_SPI3_SCK 0x600004c
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IMX8QM_SPI3_SDO_DMA_SPI3_SDO 0x600004c
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IMX8QM_SPI3_SDI_DMA_SPI3_SDI 0x600004c
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IMX8QM_SPI3_CS0_DMA_SPI3_CS0 0x600004c
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>;
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};
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};
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&lpspi0 {
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fsl,spi-num-chipselects = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
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cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>;
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status = "okay";
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flash: at45db041e@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at45", "atmel,dataflash";
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spi-max-frequency = <5000000>;
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reg = <0>;
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};
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};
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&lpspi3 {
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fsl,spi-num-chipselects = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpspi3>;
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status = "okay";
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spidev0: spi@0 {
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reg = <0>;
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compatible = "rohm,dh2228fv";
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spi-max-frequency = <30000000>;
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};
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};
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