66 lines
1.6 KiB
Plaintext
66 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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/dts-v1/;
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#include <dt-bindings/usb/pd.h>
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#include "imx8qm-mek.dts"
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/*
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* Add the PCIeA x2 lanes and PCIeB x1 lane usecase
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* hsio-cfg = <PCIEAX2PCIEBX1>
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* NOTE: In this case, the HSIO nodes contained
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* hsio-cfg = <PCIEAX1PCIEBX1SATA> would be re-configured.
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*/
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&pciea{
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ext_osc = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pciea>;
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disable-gpio = <&lsio_gpio4 9 GPIO_ACTIVE_LOW>;
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reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
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epdev_on-supply = <&epdev_on>;
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num-lanes = <2>;
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clocks = <&pciea_lpcg 0>,
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<&pciea_lpcg 1>,
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<&pciea_lpcg 2>,
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<&phyx2_lpcg 0>,
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<&phyx2_crr0_lpcg 0>,
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<&pciea_crr2_lpcg 0>,
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<&misc_crr5_lpcg 0>;
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clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
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"pcie_phy", "phy_per","pcie_per", "misc_per";
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hsio-cfg = <PCIEAX2PCIEBX1>;
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status = "okay";
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};
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&pcieb{
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ext_osc = <1>;
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clocks = <&pcieb_lpcg 0>,
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<&pcieb_lpcg 1>,
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<&pcieb_lpcg 2>,
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<&phyx1_lpcg 0>,
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<&phyx2_lpcg 0>,
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<&phyx1_crr1_lpcg 0>,
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<&pcieb_crr3_lpcg 0>,
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<&pciea_crr2_lpcg 0>,
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<&misc_crr5_lpcg 0>;
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clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
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"pcie_phy", "pcie_phy_pclk", "phy_per",
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"pcie_per", "pciex2_per", "misc_per";
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power-domains = <&pd IMX_SC_R_PCIE_B>,
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<&pd IMX_SC_R_PCIE_A>,
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<&pd IMX_SC_R_SERDES_0>,
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<&pd IMX_SC_R_SERDES_1>,
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<&pd IMX_SC_R_HSIO_GPIO>;
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power-domain-names = "pcie", "pcie_per", "pcie_phy",
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"pcie_serdes", "hsio_gpio";
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hsio-cfg = <PCIEAX2PCIEBX1>;
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status = "okay";
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};
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&sata {
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status = "disabled";
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};
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