![Ingo Molnar](/assets/img/avatar_default.png)
We are going to split <linux/sched/debug.h> out of <linux/sched.h>, which will have to be picked up from other headers and a couple of .c files. Create a trivial placeholder <linux/sched/debug.h> file that just maps to <linux/sched.h> to make this patch obviously correct and bisectable. Include the new header in the files that are going to need it. Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
818 lines
21 KiB
C
818 lines
21 KiB
C
/*
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* arch/sh/kernel/traps_64.c
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003, 2004 Paul Mundt
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* Copyright (C) 2003, 2004 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/sched.h>
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#include <linux/sched/debug.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/ptrace.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/kallsyms.h>
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#include <linux/interrupt.h>
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#include <linux/sysctl.h>
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#include <linux/module.h>
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#include <linux/perf_event.h>
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#include <linux/uaccess.h>
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#include <asm/io.h>
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#include <asm/alignment.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/fpu.h>
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static int read_opcode(reg_size_t pc, insn_size_t *result_opcode, int from_user_mode)
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{
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int get_user_error;
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unsigned long aligned_pc;
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insn_size_t opcode;
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if ((pc & 3) == 1) {
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/* SHmedia */
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aligned_pc = pc & ~3;
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if (from_user_mode) {
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if (!access_ok(VERIFY_READ, aligned_pc, sizeof(insn_size_t))) {
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get_user_error = -EFAULT;
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} else {
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get_user_error = __get_user(opcode, (insn_size_t *)aligned_pc);
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*result_opcode = opcode;
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}
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return get_user_error;
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} else {
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/* If the fault was in the kernel, we can either read
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* this directly, or if not, we fault.
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*/
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*result_opcode = *(insn_size_t *)aligned_pc;
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return 0;
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}
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} else if ((pc & 1) == 0) {
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/* SHcompact */
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/* TODO : provide handling for this. We don't really support
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user-mode SHcompact yet, and for a kernel fault, this would
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have to come from a module built for SHcompact. */
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return -EFAULT;
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} else {
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/* misaligned */
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return -EFAULT;
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}
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}
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static int address_is_sign_extended(__u64 a)
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{
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__u64 b;
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#if (NEFF == 32)
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b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
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return (b == a) ? 1 : 0;
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#else
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#error "Sign extend check only works for NEFF==32"
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#endif
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}
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/* return -1 for fault, 0 for OK */
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static int generate_and_check_address(struct pt_regs *regs,
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insn_size_t opcode,
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int displacement_not_indexed,
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int width_shift,
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__u64 *address)
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{
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__u64 base_address, addr;
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int basereg;
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switch (1 << width_shift) {
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case 1: inc_unaligned_byte_access(); break;
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case 2: inc_unaligned_word_access(); break;
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case 4: inc_unaligned_dword_access(); break;
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case 8: inc_unaligned_multi_access(); break;
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}
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basereg = (opcode >> 20) & 0x3f;
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base_address = regs->regs[basereg];
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if (displacement_not_indexed) {
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__s64 displacement;
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displacement = (opcode >> 10) & 0x3ff;
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displacement = sign_extend64(displacement, 9);
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addr = (__u64)((__s64)base_address + (displacement << width_shift));
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} else {
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__u64 offset;
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int offsetreg;
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offsetreg = (opcode >> 10) & 0x3f;
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offset = regs->regs[offsetreg];
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addr = base_address + offset;
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}
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/* Check sign extended */
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if (!address_is_sign_extended(addr))
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return -1;
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/* Check accessible. For misaligned access in the kernel, assume the
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address is always accessible (and if not, just fault when the
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load/store gets done.) */
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if (user_mode(regs)) {
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inc_unaligned_user_access();
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if (addr >= TASK_SIZE)
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return -1;
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} else
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inc_unaligned_kernel_access();
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*address = addr;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, addr);
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unaligned_fixups_notify(current, opcode, regs);
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return 0;
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}
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static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
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{
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unsigned short x;
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unsigned char *p, *q;
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p = (unsigned char *) (int) address;
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q = (unsigned char *) &x;
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q[0] = p[0];
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q[1] = p[1];
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if (do_sign_extend) {
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*result = (__u64)(__s64) *(short *) &x;
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} else {
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*result = (__u64) x;
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}
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}
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static void misaligned_kernel_word_store(__u64 address, __u64 value)
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{
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unsigned short x;
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unsigned char *p, *q;
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p = (unsigned char *) (int) address;
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q = (unsigned char *) &x;
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x = (__u16) value;
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p[0] = q[0];
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p[1] = q[1];
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}
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static int misaligned_load(struct pt_regs *regs,
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insn_size_t opcode,
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int displacement_not_indexed,
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int width_shift,
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int do_sign_extend)
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{
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/* Return -1 for a fault, 0 for OK */
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int error;
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int destreg;
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__u64 address;
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error = generate_and_check_address(regs, opcode,
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displacement_not_indexed, width_shift, &address);
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if (error < 0)
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return error;
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destreg = (opcode >> 4) & 0x3f;
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if (user_mode(regs)) {
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__u64 buffer;
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if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
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return -1;
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}
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if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
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return -1; /* fault */
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}
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switch (width_shift) {
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case 1:
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if (do_sign_extend) {
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regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
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} else {
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regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
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}
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break;
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case 2:
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regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
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break;
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case 3:
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regs->regs[destreg] = buffer;
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break;
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default:
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printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
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width_shift, (unsigned long) regs->pc);
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break;
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}
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} else {
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/* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
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__u64 lo, hi;
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switch (width_shift) {
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case 1:
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misaligned_kernel_word_load(address, do_sign_extend, ®s->regs[destreg]);
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break;
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case 2:
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asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
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asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
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regs->regs[destreg] = lo | hi;
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break;
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case 3:
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asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
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asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
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regs->regs[destreg] = lo | hi;
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break;
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default:
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printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
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width_shift, (unsigned long) regs->pc);
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break;
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}
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}
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return 0;
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}
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static int misaligned_store(struct pt_regs *regs,
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insn_size_t opcode,
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int displacement_not_indexed,
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int width_shift)
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{
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/* Return -1 for a fault, 0 for OK */
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int error;
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int srcreg;
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__u64 address;
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error = generate_and_check_address(regs, opcode,
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displacement_not_indexed, width_shift, &address);
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if (error < 0)
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return error;
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srcreg = (opcode >> 4) & 0x3f;
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if (user_mode(regs)) {
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__u64 buffer;
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if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
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return -1;
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}
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switch (width_shift) {
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case 1:
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*(__u16 *) &buffer = (__u16) regs->regs[srcreg];
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break;
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case 2:
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*(__u32 *) &buffer = (__u32) regs->regs[srcreg];
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break;
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case 3:
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buffer = regs->regs[srcreg];
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break;
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default:
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printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
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width_shift, (unsigned long) regs->pc);
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break;
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}
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if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
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return -1; /* fault */
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}
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} else {
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/* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
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__u64 val = regs->regs[srcreg];
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switch (width_shift) {
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case 1:
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misaligned_kernel_word_store(address, val);
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break;
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case 2:
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asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
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asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
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break;
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case 3:
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asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
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asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
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break;
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default:
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printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
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width_shift, (unsigned long) regs->pc);
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break;
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}
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}
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return 0;
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}
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/* Never need to fix up misaligned FPU accesses within the kernel since that's a real
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error. */
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static int misaligned_fpu_load(struct pt_regs *regs,
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insn_size_t opcode,
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int displacement_not_indexed,
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int width_shift,
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int do_paired_load)
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{
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/* Return -1 for a fault, 0 for OK */
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int error;
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int destreg;
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__u64 address;
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error = generate_and_check_address(regs, opcode,
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displacement_not_indexed, width_shift, &address);
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if (error < 0)
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return error;
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destreg = (opcode >> 4) & 0x3f;
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if (user_mode(regs)) {
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__u64 buffer;
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__u32 buflo, bufhi;
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if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
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return -1;
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}
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if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
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return -1; /* fault */
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}
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/* 'current' may be the current owner of the FPU state, so
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context switch the registers into memory so they can be
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indexed by register number. */
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if (last_task_used_math == current) {
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enable_fpu();
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save_fpu(current);
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disable_fpu();
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last_task_used_math = NULL;
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regs->sr |= SR_FD;
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}
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buflo = *(__u32*) &buffer;
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bufhi = *(1 + (__u32*) &buffer);
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switch (width_shift) {
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case 2:
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current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
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break;
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case 3:
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if (do_paired_load) {
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current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
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current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
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} else {
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#if defined(CONFIG_CPU_LITTLE_ENDIAN)
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current->thread.xstate->hardfpu.fp_regs[destreg] = bufhi;
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current->thread.xstate->hardfpu.fp_regs[destreg+1] = buflo;
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#else
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current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
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current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
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#endif
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}
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break;
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default:
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printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
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width_shift, (unsigned long) regs->pc);
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break;
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}
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return 0;
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} else {
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die ("Misaligned FPU load inside kernel", regs, 0);
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return -1;
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}
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}
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static int misaligned_fpu_store(struct pt_regs *regs,
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insn_size_t opcode,
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int displacement_not_indexed,
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int width_shift,
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int do_paired_load)
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{
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/* Return -1 for a fault, 0 for OK */
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int error;
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int srcreg;
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__u64 address;
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error = generate_and_check_address(regs, opcode,
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displacement_not_indexed, width_shift, &address);
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if (error < 0)
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return error;
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srcreg = (opcode >> 4) & 0x3f;
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if (user_mode(regs)) {
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__u64 buffer;
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/* Initialise these to NaNs. */
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__u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
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if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
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return -1;
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}
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/* 'current' may be the current owner of the FPU state, so
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context switch the registers into memory so they can be
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indexed by register number. */
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if (last_task_used_math == current) {
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enable_fpu();
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save_fpu(current);
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disable_fpu();
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last_task_used_math = NULL;
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regs->sr |= SR_FD;
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}
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switch (width_shift) {
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case 2:
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buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
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break;
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case 3:
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if (do_paired_load) {
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buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
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bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
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} else {
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#if defined(CONFIG_CPU_LITTLE_ENDIAN)
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bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg];
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buflo = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
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#else
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buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
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bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
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#endif
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}
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break;
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default:
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printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
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width_shift, (unsigned long) regs->pc);
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break;
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}
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*(__u32*) &buffer = buflo;
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*(1 + (__u32*) &buffer) = bufhi;
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if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
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return -1; /* fault */
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}
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return 0;
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} else {
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die ("Misaligned FPU load inside kernel", regs, 0);
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return -1;
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}
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}
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static int misaligned_fixup(struct pt_regs *regs)
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{
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insn_size_t opcode;
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int error;
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int major, minor;
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unsigned int user_action;
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user_action = unaligned_user_action();
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if (!(user_action & UM_FIXUP))
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return -1;
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error = read_opcode(regs->pc, &opcode, user_mode(regs));
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if (error < 0) {
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return error;
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}
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major = (opcode >> 26) & 0x3f;
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minor = (opcode >> 16) & 0xf;
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switch (major) {
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case (0x84>>2): /* LD.W */
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error = misaligned_load(regs, opcode, 1, 1, 1);
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break;
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case (0xb0>>2): /* LD.UW */
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error = misaligned_load(regs, opcode, 1, 1, 0);
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break;
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case (0x88>>2): /* LD.L */
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error = misaligned_load(regs, opcode, 1, 2, 1);
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break;
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case (0x8c>>2): /* LD.Q */
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error = misaligned_load(regs, opcode, 1, 3, 0);
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break;
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case (0xa4>>2): /* ST.W */
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error = misaligned_store(regs, opcode, 1, 1);
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break;
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case (0xa8>>2): /* ST.L */
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error = misaligned_store(regs, opcode, 1, 2);
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break;
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case (0xac>>2): /* ST.Q */
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error = misaligned_store(regs, opcode, 1, 3);
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break;
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|
|
case (0x40>>2): /* indexed loads */
|
|
switch (minor) {
|
|
case 0x1: /* LDX.W */
|
|
error = misaligned_load(regs, opcode, 0, 1, 1);
|
|
break;
|
|
case 0x5: /* LDX.UW */
|
|
error = misaligned_load(regs, opcode, 0, 1, 0);
|
|
break;
|
|
case 0x2: /* LDX.L */
|
|
error = misaligned_load(regs, opcode, 0, 2, 1);
|
|
break;
|
|
case 0x3: /* LDX.Q */
|
|
error = misaligned_load(regs, opcode, 0, 3, 0);
|
|
break;
|
|
default:
|
|
error = -1;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case (0x60>>2): /* indexed stores */
|
|
switch (minor) {
|
|
case 0x1: /* STX.W */
|
|
error = misaligned_store(regs, opcode, 0, 1);
|
|
break;
|
|
case 0x2: /* STX.L */
|
|
error = misaligned_store(regs, opcode, 0, 2);
|
|
break;
|
|
case 0x3: /* STX.Q */
|
|
error = misaligned_store(regs, opcode, 0, 3);
|
|
break;
|
|
default:
|
|
error = -1;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case (0x94>>2): /* FLD.S */
|
|
error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
|
|
break;
|
|
case (0x98>>2): /* FLD.P */
|
|
error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
|
|
break;
|
|
case (0x9c>>2): /* FLD.D */
|
|
error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
|
|
break;
|
|
case (0x1c>>2): /* floating indexed loads */
|
|
switch (minor) {
|
|
case 0x8: /* FLDX.S */
|
|
error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
|
|
break;
|
|
case 0xd: /* FLDX.P */
|
|
error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
|
|
break;
|
|
case 0x9: /* FLDX.D */
|
|
error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
|
|
break;
|
|
default:
|
|
error = -1;
|
|
break;
|
|
}
|
|
break;
|
|
case (0xb4>>2): /* FLD.S */
|
|
error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
|
|
break;
|
|
case (0xb8>>2): /* FLD.P */
|
|
error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
|
|
break;
|
|
case (0xbc>>2): /* FLD.D */
|
|
error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
|
|
break;
|
|
case (0x3c>>2): /* floating indexed stores */
|
|
switch (minor) {
|
|
case 0x8: /* FSTX.S */
|
|
error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
|
|
break;
|
|
case 0xd: /* FSTX.P */
|
|
error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
|
|
break;
|
|
case 0x9: /* FSTX.D */
|
|
error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
|
|
break;
|
|
default:
|
|
error = -1;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
/* Fault */
|
|
error = -1;
|
|
break;
|
|
}
|
|
|
|
if (error < 0) {
|
|
return error;
|
|
} else {
|
|
regs->pc += 4; /* Skip the instruction that's just been emulated */
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void do_unhandled_exception(int signr, char *str, unsigned long error,
|
|
struct pt_regs *regs)
|
|
{
|
|
if (user_mode(regs))
|
|
force_sig(signr, current);
|
|
|
|
die_if_no_fixup(str, regs, error);
|
|
}
|
|
|
|
#define DO_ERROR(signr, str, name) \
|
|
asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
|
|
{ \
|
|
do_unhandled_exception(signr, str, error_code, regs); \
|
|
}
|
|
|
|
DO_ERROR(SIGILL, "illegal slot instruction", illegal_slot_inst)
|
|
DO_ERROR(SIGSEGV, "address error (exec)", address_error_exec)
|
|
|
|
#if defined(CONFIG_SH64_ID2815_WORKAROUND)
|
|
|
|
#define OPCODE_INVALID 0
|
|
#define OPCODE_USER_VALID 1
|
|
#define OPCODE_PRIV_VALID 2
|
|
|
|
/* getcon/putcon - requires checking which control register is referenced. */
|
|
#define OPCODE_CTRL_REG 3
|
|
|
|
/* Table of valid opcodes for SHmedia mode.
|
|
Form a 10-bit value by concatenating the major/minor opcodes i.e.
|
|
opcode[31:26,20:16]. The 6 MSBs of this value index into the following
|
|
array. The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
|
|
LSBs==4'b0000 etc). */
|
|
static unsigned long shmedia_opcode_table[64] = {
|
|
0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
|
|
0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
|
|
0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
|
|
0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
|
|
0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
|
|
0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
|
|
0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
|
|
0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
|
|
};
|
|
|
|
/* Workaround SH5-101 cut2 silicon defect #2815 :
|
|
in some situations, inter-mode branches from SHcompact -> SHmedia
|
|
which should take ITLBMISS or EXECPROT exceptions at the target
|
|
falsely take RESINST at the target instead. */
|
|
void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
|
|
{
|
|
insn_size_t opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
|
|
unsigned long pc, aligned_pc;
|
|
unsigned long index, shift;
|
|
unsigned long major, minor, combined;
|
|
unsigned long reserved_field;
|
|
int opcode_state;
|
|
int get_user_error;
|
|
int signr = SIGILL;
|
|
char *exception_name = "reserved_instruction";
|
|
|
|
pc = regs->pc;
|
|
|
|
/* SHcompact is not handled */
|
|
if (unlikely((pc & 3) == 0))
|
|
goto out;
|
|
|
|
/* SHmedia : check for defect. This requires executable vmas
|
|
to be readable too. */
|
|
aligned_pc = pc & ~3;
|
|
if (!access_ok(VERIFY_READ, aligned_pc, sizeof(insn_size_t)))
|
|
get_user_error = -EFAULT;
|
|
else
|
|
get_user_error = __get_user(opcode, (insn_size_t *)aligned_pc);
|
|
|
|
if (get_user_error < 0) {
|
|
/*
|
|
* Error trying to read opcode. This typically means a
|
|
* real fault, not a RESINST any more. So change the
|
|
* codes.
|
|
*/
|
|
exception_name = "address error (exec)";
|
|
signr = SIGSEGV;
|
|
goto out;
|
|
}
|
|
|
|
/* These bits are currently reserved as zero in all valid opcodes */
|
|
reserved_field = opcode & 0xf;
|
|
if (unlikely(reserved_field))
|
|
goto out; /* invalid opcode */
|
|
|
|
major = (opcode >> 26) & 0x3f;
|
|
minor = (opcode >> 16) & 0xf;
|
|
combined = (major << 4) | minor;
|
|
index = major;
|
|
shift = minor << 1;
|
|
opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
|
|
switch (opcode_state) {
|
|
case OPCODE_INVALID:
|
|
/* Trap. */
|
|
break;
|
|
case OPCODE_USER_VALID:
|
|
/*
|
|
* Restart the instruction: the branch to the instruction
|
|
* will now be from an RTE not from SHcompact so the
|
|
* silicon defect won't be triggered.
|
|
*/
|
|
return;
|
|
case OPCODE_PRIV_VALID:
|
|
if (!user_mode(regs)) {
|
|
/*
|
|
* Should only ever get here if a module has
|
|
* SHcompact code inside it. If so, the same fix
|
|
* up is needed.
|
|
*/
|
|
return; /* same reason */
|
|
}
|
|
|
|
/*
|
|
* Otherwise, user mode trying to execute a privileged
|
|
* instruction - fall through to trap.
|
|
*/
|
|
break;
|
|
case OPCODE_CTRL_REG:
|
|
/* If in privileged mode, return as above. */
|
|
if (!user_mode(regs))
|
|
return;
|
|
|
|
/* In user mode ... */
|
|
if (combined == 0x9f) { /* GETCON */
|
|
unsigned long regno = (opcode >> 20) & 0x3f;
|
|
|
|
if (regno >= 62)
|
|
return;
|
|
|
|
/* reserved/privileged control register => trap */
|
|
} else if (combined == 0x1bf) { /* PUTCON */
|
|
unsigned long regno = (opcode >> 4) & 0x3f;
|
|
|
|
if (regno >= 62)
|
|
return;
|
|
|
|
/* reserved/privileged control register => trap */
|
|
}
|
|
|
|
break;
|
|
default:
|
|
/* Fall through to trap. */
|
|
break;
|
|
}
|
|
|
|
out:
|
|
do_unhandled_exception(signr, exception_name, error_code, regs);
|
|
}
|
|
|
|
#else /* CONFIG_SH64_ID2815_WORKAROUND */
|
|
|
|
/* If the workaround isn't needed, this is just a straightforward reserved
|
|
instruction */
|
|
DO_ERROR(SIGILL, "reserved instruction", reserved_inst)
|
|
|
|
#endif /* CONFIG_SH64_ID2815_WORKAROUND */
|
|
|
|
/* Called with interrupts disabled */
|
|
asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
|
|
{
|
|
die_if_kernel("exception", regs, ex);
|
|
}
|
|
|
|
asmlinkage int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
|
|
{
|
|
/* Syscall debug */
|
|
printk("System call ID error: [0x1#args:8 #syscall:16 0x%lx]\n", scId);
|
|
|
|
die_if_kernel("unknown trapa", regs, scId);
|
|
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/* Implement misaligned load/store handling for kernel (and optionally for user
|
|
mode too). Limitation : only SHmedia mode code is handled - there is no
|
|
handling at all for misaligned accesses occurring in SHcompact code yet. */
|
|
|
|
asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
|
|
{
|
|
if (misaligned_fixup(regs) < 0)
|
|
do_unhandled_exception(SIGSEGV, "address error(load)",
|
|
error_code, regs);
|
|
}
|
|
|
|
asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
|
|
{
|
|
if (misaligned_fixup(regs) < 0)
|
|
do_unhandled_exception(SIGSEGV, "address error(store)",
|
|
error_code, regs);
|
|
}
|
|
|
|
asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
|
|
{
|
|
u64 peek_real_address_q(u64 addr);
|
|
u64 poke_real_address_q(u64 addr, u64 val);
|
|
unsigned long long DM_EXP_CAUSE_PHY = 0x0c100010;
|
|
unsigned long long exp_cause;
|
|
/* It's not worth ioremapping the debug module registers for the amount
|
|
of access we make to them - just go direct to their physical
|
|
addresses. */
|
|
exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
|
|
if (exp_cause & ~4)
|
|
printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
|
|
(unsigned long)(exp_cause & 0xffffffff));
|
|
show_state();
|
|
/* Clear all DEBUGINT causes */
|
|
poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
|
|
}
|
|
|
|
void per_cpu_trap_init(void)
|
|
{
|
|
/* Nothing to do for now, VBR initialization later. */
|
|
}
|