44d8311272
This patch removes typedef for _FLASH_SECTOR_INFO because it is not being used. Signed-off-by: Kevin McKinney <klmckinney1@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
287 lines
9.4 KiB
C
287 lines
9.4 KiB
C
/***************************************************************************************
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*
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* Copyright (c) Beceem Communications Inc.
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*
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* Module Name:
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* NVM.h
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*
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* Abstract:
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* This file has the prototypes,preprocessors and definitions various NVM libraries.
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*
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*
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* Revision History:
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* Who When What
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* -------- -------- ----------------------------------------------
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* Name Date Created/reviewed/modified
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*
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* Notes:
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*
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****************************************************************************************/
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#ifndef _NVM_H_
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#define _NVM_H_
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struct bcm_flash_cs_info {
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u32 MagicNumber;
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/* let the magic number be 0xBECE-F1A5 - F1A5 for "flas-h" */
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u32 FlashLayoutVersion;
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u32 ISOImageVersion;
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u32 SCSIFirmwareVersion;
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u32 OffsetFromZeroForPart1ISOImage;
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u32 OffsetFromZeroForScsiFirmware;
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u32 SizeOfScsiFirmware;
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u32 OffsetFromZeroForPart2ISOImage;
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u32 OffsetFromZeroForCalibrationStart;
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u32 OffsetFromZeroForCalibrationEnd;
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u32 OffsetFromZeroForVSAStart;
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u32 OffsetFromZeroForVSAEnd;
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u32 OffsetFromZeroForControlSectionStart;
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u32 OffsetFromZeroForControlSectionData;
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u32 CDLessInactivityTimeout;
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u32 NewImageSignature;
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u32 FlashSectorSizeSig;
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u32 FlashSectorSize;
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u32 FlashWriteSupportSize;
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u32 TotalFlashSize;
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u32 FlashBaseAddr;
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u32 FlashPartMaxSize;
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u32 IsCDLessDeviceBootSig;
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/* MSC Timeout after reset to switch from MSC to NW Mode */
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u32 MassStorageTimeout;
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};
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#define FLASH2X_TOTAL_SIZE (64 * 1024 * 1024)
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#define DEFAULT_SECTOR_SIZE (64 * 1024)
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struct bcm_flash2x_cs_info {
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/* magic number as 0xBECE-F1A5 - F1A5 for "flas-h" */
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u32 MagicNumber;
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u32 FlashLayoutVersion;
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u32 ISOImageVersion;
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u32 SCSIFirmwareVersion;
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u32 OffsetFromZeroForPart1ISOImage;
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u32 OffsetFromZeroForScsiFirmware;
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u32 SizeOfScsiFirmware;
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u32 OffsetFromZeroForPart2ISOImage;
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u32 OffsetFromZeroForDSDStart;
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u32 OffsetFromZeroForDSDEnd;
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u32 OffsetFromZeroForVSAStart;
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u32 OffsetFromZeroForVSAEnd;
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u32 OffsetFromZeroForControlSectionStart;
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u32 OffsetFromZeroForControlSectionData;
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/* NO Data Activity timeout to switch from MSC to NW Mode */
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u32 CDLessInactivityTimeout;
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u32 NewImageSignature;
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u32 FlashSectorSizeSig;
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u32 FlashSectorSize;
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u32 FlashWriteSupportSize;
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u32 TotalFlashSize;
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u32 FlashBaseAddr;
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u32 FlashPartMaxSize;
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u32 IsCDLessDeviceBootSig;
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/* MSC Timeout after reset to switch from MSC to NW Mode */
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u32 MassStorageTimeout;
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/* Flash Map 2.0 Field */
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u32 OffsetISOImage1Part1Start;
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u32 OffsetISOImage1Part1End;
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u32 OffsetISOImage1Part2Start;
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u32 OffsetISOImage1Part2End;
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u32 OffsetISOImage1Part3Start;
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u32 OffsetISOImage1Part3End;
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u32 OffsetISOImage2Part1Start;
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u32 OffsetISOImage2Part1End;
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u32 OffsetISOImage2Part2Start;
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u32 OffsetISOImage2Part2End;
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u32 OffsetISOImage2Part3Start;
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u32 OffsetISOImage2Part3End;
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/* DSD Header offset from start of DSD */
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u32 OffsetFromDSDStartForDSDHeader;
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u32 OffsetFromZeroForDSD1Start;
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u32 OffsetFromZeroForDSD1End;
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u32 OffsetFromZeroForDSD2Start;
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u32 OffsetFromZeroForDSD2End;
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u32 OffsetFromZeroForVSA1Start;
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u32 OffsetFromZeroForVSA1End;
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u32 OffsetFromZeroForVSA2Start;
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u32 OffsetFromZeroForVSA2End;
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/*
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* ACCESS_BITS_PER_SECTOR 2
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* ACCESS_RW 0
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* ACCESS_RO 1
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* ACCESS_RESVD 2
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* ACCESS_RESVD 3
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*/
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u32 SectorAccessBitMap[FLASH2X_TOTAL_SIZE / (DEFAULT_SECTOR_SIZE * 16)];
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/* All expansions to the control data structure should add here */
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};
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struct bcm_vendor_section_info {
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u32 OffsetFromZeroForSectionStart;
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u32 OffsetFromZeroForSectionEnd;
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u32 AccessFlags;
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u32 Reserved[16];
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};
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struct bcm_flash2x_vendor_info {
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struct bcm_vendor_section_info VendorSection[TOTAL_SECTIONS];
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u32 Reserved[16];
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};
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struct bcm_dsd_header {
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u32 DSDImageSize;
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u32 DSDImageCRC;
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u32 DSDImagePriority;
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/* We should not consider right now. Reading reserve is worthless. */
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u32 Reserved[252]; /* Resvd for DSD Header */
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u32 DSDImageMagicNumber;
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};
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struct bcm_iso_header {
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u32 ISOImageMagicNumber;
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u32 ISOImageSize;
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u32 ISOImageCRC;
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u32 ISOImagePriority;
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/* We should not consider right now. Reading reserve is worthless. */
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u32 Reserved[60]; /* Resvd for ISO Header extension */
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};
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#define EEPROM_BEGIN_CIS (0)
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#define EEPROM_BEGIN_NON_CIS (0x200)
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#define EEPROM_END (0x2000)
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#define INIT_PARAMS_SIGNATURE (0x95a7a597)
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#define MAX_INIT_PARAMS_LENGTH (2048)
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#define MAC_ADDRESS_OFFSET 0x200
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#define INIT_PARAMS_1_SIGNATURE_ADDRESS EEPROM_BEGIN_NON_CIS
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#define INIT_PARAMS_1_DATA_ADDRESS (INIT_PARAMS_1_SIGNATURE_ADDRESS+16)
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#define INIT_PARAMS_1_MACADDRESS_ADDRESS (MAC_ADDRESS_OFFSET)
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#define INIT_PARAMS_1_LENGTH_ADDRESS (INIT_PARAMS_1_SIGNATURE_ADDRESS+4)
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#define INIT_PARAMS_2_SIGNATURE_ADDRESS (EEPROM_BEGIN_NON_CIS + 2048 + 16)
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#define INIT_PARAMS_2_DATA_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS + 16)
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#define INIT_PARAMS_2_MACADDRESS_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS + 8)
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#define INIT_PARAMS_2_LENGTH_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS + 4)
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#define EEPROM_SPI_DEV_CONFIG_REG 0x0F003000
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#define EEPROM_SPI_Q_STATUS1_REG 0x0F003004
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#define EEPROM_SPI_Q_STATUS1_MASK_REG 0x0F00300C
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#define EEPROM_SPI_Q_STATUS_REG 0x0F003008
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#define EEPROM_CMDQ_SPI_REG 0x0F003018
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#define EEPROM_WRITE_DATAQ_REG 0x0F00301C
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#define EEPROM_READ_DATAQ_REG 0x0F003020
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#define SPI_FLUSH_REG 0x0F00304C
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#define EEPROM_WRITE_ENABLE 0x06000000
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#define EEPROM_READ_STATUS_REGISTER 0x05000000
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#define EEPROM_16_BYTE_PAGE_WRITE 0xFA000000
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#define EEPROM_WRITE_QUEUE_EMPTY 0x00001000
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#define EEPROM_WRITE_QUEUE_AVAIL 0x00002000
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#define EEPROM_WRITE_QUEUE_FULL 0x00004000
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#define EEPROM_16_BYTE_PAGE_READ 0xFB000000
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#define EEPROM_4_BYTE_PAGE_READ 0x3B000000
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#define EEPROM_CMD_QUEUE_FLUSH 0x00000001
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#define EEPROM_WRITE_QUEUE_FLUSH 0x00000002
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#define EEPROM_READ_QUEUE_FLUSH 0x00000004
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#define EEPROM_ETH_QUEUE_FLUSH 0x00000008
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#define EEPROM_ALL_QUEUE_FLUSH 0x0000000f
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#define EEPROM_READ_ENABLE 0x06000000
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#define EEPROM_16_BYTE_PAGE_WRITE 0xFA000000
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#define EEPROM_READ_DATA_FULL 0x00000010
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#define EEPROM_READ_DATA_AVAIL 0x00000020
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#define EEPROM_READ_QUEUE_EMPTY 0x00000002
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#define EEPROM_CMD_QUEUE_EMPTY 0x00000100
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#define EEPROM_CMD_QUEUE_AVAIL 0x00000200
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#define EEPROM_CMD_QUEUE_FULL 0x00000400
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/* Most EEPROM status register bit 0 indicates if the EEPROM is busy
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* with a write if set 1. See the details of the EEPROM Status Register
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* in the EEPROM data sheet.
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*/
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#define EEPROM_STATUS_REG_WRITE_BUSY 0x00000001
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/* We will have 1 mSec for every RETRIES_PER_DELAY count and have a max attempts of MAX_EEPROM_RETRIES
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* This will give us 80 mSec minimum of delay = 80mSecs
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*/
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#define MAX_EEPROM_RETRIES 80
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#define RETRIES_PER_DELAY 64
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#define MAX_RW_SIZE 0x10
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#define MAX_READ_SIZE 0x10
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#define MAX_SECTOR_SIZE (512 * 1024)
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#define MIN_SECTOR_SIZE (1024)
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#define FLASH_SECTOR_SIZE_OFFSET 0xEFFFC
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#define FLASH_SECTOR_SIZE_SIG_OFFSET 0xEFFF8
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#define FLASH_SECTOR_SIZE_SIG 0xCAFEBABE
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#define FLASH_CS_INFO_START_ADDR 0xFF0000
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#define FLASH_CONTROL_STRUCT_SIGNATURE 0xBECEF1A5
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#define SCSI_FIRMWARE_MAJOR_VERSION 0x1
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#define SCSI_FIRMWARE_MINOR_VERSION 0x5
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#define BYTE_WRITE_SUPPORT 0x1
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#define FLASH_AUTO_INIT_BASE_ADDR 0xF00000
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#define FLASH_CONTIGIOUS_START_ADDR_AFTER_INIT 0x1C000000
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#define FLASH_CONTIGIOUS_START_ADDR_BEFORE_INIT 0x1F000000
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#define FLASH_CONTIGIOUS_START_ADDR_BCS350 0x08000000
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#define FLASH_CONTIGIOUS_END_ADDR_BCS350 0x08FFFFFF
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#define FLASH_SIZE_ADDR 0xFFFFEC
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#define FLASH_SPI_CMDQ_REG 0xAF003040
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#define FLASH_SPI_WRITEQ_REG 0xAF003044
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#define FLASH_SPI_READQ_REG 0xAF003048
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#define FLASH_CONFIG_REG 0xAF003050
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#define FLASH_GPIO_CONFIG_REG 0xAF000030
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#define FLASH_CMD_WRITE_ENABLE 0x06
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#define FLASH_CMD_READ_ENABLE 0x03
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#define FLASH_CMD_RESET_WRITE_ENABLE 0x04
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#define FLASH_CMD_STATUS_REG_READ 0x05
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#define FLASH_CMD_STATUS_REG_WRITE 0x01
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#define FLASH_CMD_READ_ID 0x9F
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#define PAD_SELECT_REGISTER 0xAF000410
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#define FLASH_PART_SST25VF080B 0xBF258E
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#define EEPROM_CAL_DATA_INTERNAL_LOC 0xbFB00008
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#define EEPROM_CALPARAM_START 0x200
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#define EEPROM_SIZE_OFFSET 524
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/* As Read/Write time vaires from 1.5 to 3.0 ms.
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* so After Ignoring the rdm/wrm time(that is dependent on many factor like interface etc.),
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* here time calculated meets the worst case delay, 3.0 ms
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*/
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#define MAX_FLASH_RETRIES 4
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#define FLASH_PER_RETRIES_DELAY 16
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#define EEPROM_MAX_CAL_AREA_SIZE 0xF0000
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#define BECM ntohl(0x4245434d)
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#define FLASH_2X_MAJOR_NUMBER 0x2
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#define DSD_IMAGE_MAGIC_NUMBER 0xBECE0D5D
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#define ISO_IMAGE_MAGIC_NUMBER 0xBECE0150
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#define NON_CDLESS_DEVICE_BOOT_SIG 0xBECEB007
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#define MINOR_VERSION(x) ((x >> 16) & 0xFFFF)
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#define MAJOR_VERSION(x) (x & 0xFFFF)
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#define CORRUPTED_PATTERN 0x0
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#define UNINIT_PTR_IN_CS 0xBBBBDDDD
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#define VENDOR_PTR_IN_CS 0xAAAACCCC
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#define FLASH2X_SECTION_PRESENT (1 << 0)
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#define FLASH2X_SECTION_VALID (1 << 1)
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#define FLASH2X_SECTION_RO (1 << 2)
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#define FLASH2X_SECTION_ACT (1 << 3)
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#define SECTOR_IS_NOT_WRITABLE STATUS_FAILURE
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#define INVALID_OFFSET STATUS_FAILURE
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#define INVALID_SECTION STATUS_FAILURE
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#define SECTOR_1K 1024
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#define SECTOR_64K (64 * SECTOR_1K)
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#define SECTOR_128K (2 * SECTOR_64K)
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#define SECTOR_256k (2 * SECTOR_128K)
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#define SECTOR_512K (2 * SECTOR_256k)
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#define FLASH_PART_SIZE (16 * 1024 * 1024)
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#define RESET_CHIP_SELECT -1
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#define CHIP_SELECT_BIT12 12
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#define SECTOR_READWRITE_PERMISSION 0
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#define SECTOR_READONLY 1
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#define SIGNATURE_SIZE 4
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#define DEFAULT_BUFF_SIZE 0x10000
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#define FIELD_OFFSET_IN_HEADER(HeaderPointer, Field) ((u8 *)&((HeaderPointer)(NULL))->Field - (u8 *)(NULL))
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#endif
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