08dbd0f8ef
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 94 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141334.043630402@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*/
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#ifndef MSM_IOMMU_H
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#define MSM_IOMMU_H
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#include <linux/interrupt.h>
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#include <linux/iommu.h>
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#include <linux/clk.h>
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/* Sharability attributes of MSM IOMMU mappings */
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#define MSM_IOMMU_ATTR_NON_SH 0x0
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#define MSM_IOMMU_ATTR_SH 0x4
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/* Cacheability attributes of MSM IOMMU mappings */
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#define MSM_IOMMU_ATTR_NONCACHED 0x0
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#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
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#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
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#define MSM_IOMMU_ATTR_CACHED_WT 0x3
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/* Mask for the cache policy attribute */
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#define MSM_IOMMU_CP_MASK 0x03
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/* Maximum number of Machine IDs that we are allowing to be mapped to the same
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* context bank. The number of MIDs mapped to the same CB does not affect
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* performance, but there is a practical limit on how many distinct MIDs may
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* be present. These mappings are typically determined at design time and are
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* not expected to change at run time.
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*/
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#define MAX_NUM_MIDS 32
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/* Maximum number of context banks that can be present in IOMMU */
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#define IOMMU_MAX_CBS 128
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/**
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* struct msm_iommu_dev - a single IOMMU hardware instance
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* ncb Number of context banks present on this IOMMU HW instance
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* dev: IOMMU device
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* irq: Interrupt number
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* clk: The bus clock for this IOMMU hardware instance
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* pclk: The clock for the IOMMU bus interconnect
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* dev_node: list head in qcom_iommu_device_list
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* dom_node: list head for domain
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* ctx_list: list of 'struct msm_iommu_ctx_dev'
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* context_map: Bitmap to track allocated context banks
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*/
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struct msm_iommu_dev {
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void __iomem *base;
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int ncb;
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struct device *dev;
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int irq;
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struct clk *clk;
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struct clk *pclk;
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struct list_head dev_node;
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struct list_head dom_node;
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struct list_head ctx_list;
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DECLARE_BITMAP(context_map, IOMMU_MAX_CBS);
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struct iommu_device iommu;
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};
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/**
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* struct msm_iommu_ctx_dev - an IOMMU context bank instance
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* of_node node ptr of client device
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* num Index of this context bank within the hardware
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* mids List of Machine IDs that are to be mapped into this context
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* bank, terminated by -1. The MID is a set of signals on the
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* AXI bus that identifies the function associated with a specific
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* memory request. (See ARM spec).
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* num_mids Total number of mids
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* node list head in ctx_list
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*/
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struct msm_iommu_ctx_dev {
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struct device_node *of_node;
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int num;
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int mids[MAX_NUM_MIDS];
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int num_mids;
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struct list_head list;
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};
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/*
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* Interrupt handler for the IOMMU context fault interrupt. Hooking the
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* interrupt is not supported in the API yet, but this will print an error
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* message and dump useful IOMMU registers.
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*/
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irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
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#endif
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