![Suresh Siddha](/assets/img/avatar_default.png)
Impact: fix wrong cache sharing detection on platforms supporting > 8 bit apicid's In the presence of extended topology eumeration leaf 0xb provided by cpuid, 32bit extended initial_apicid in cpuinfo_x86 struct will be updated by detect_extended_topology(). At this instance, we should also reinit the apicid (which could also potentially be extended to 32bit). With out this there will potentially be duplicate apicid's populated in the per cpu's cpuinfo_x86 struct, resulting in wrong cache sharing topology etc detected by init_intel_cacheinfo(). Reported-by: Dimitri Sivanich <sivanich@sgi.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Acked-by: Dimitri Sivanich <sivanich@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: <stable@kernel.org>
180 lines
4.2 KiB
C
180 lines
4.2 KiB
C
/*
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* Routines to indentify additional cpu features that are scattered in
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* cpuid space.
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*/
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#include <linux/cpu.h>
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#include <asm/pat.h>
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#include <asm/processor.h>
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#include <mach_apic.h>
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struct cpuid_bit {
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u16 feature;
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u8 reg;
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u8 bit;
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u32 level;
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};
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enum cpuid_regs {
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CR_EAX = 0,
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CR_ECX,
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CR_EDX,
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CR_EBX
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};
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void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
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{
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u32 max_level;
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u32 regs[4];
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const struct cpuid_bit *cb;
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static const struct cpuid_bit cpuid_bits[] = {
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{ X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },
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{ 0, 0, 0, 0 }
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};
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for (cb = cpuid_bits; cb->feature; cb++) {
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/* Verify that the level is valid */
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max_level = cpuid_eax(cb->level & 0xffff0000);
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if (max_level < cb->level ||
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max_level > (cb->level | 0xffff))
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continue;
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cpuid(cb->level, ®s[CR_EAX], ®s[CR_EBX],
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®s[CR_ECX], ®s[CR_EDX]);
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if (regs[cb->reg] & (1 << cb->bit))
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set_cpu_cap(c, cb->feature);
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}
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}
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/* leaf 0xb SMT level */
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#define SMT_LEVEL 0
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/* leaf 0xb sub-leaf types */
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#define INVALID_TYPE 0
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#define SMT_TYPE 1
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#define CORE_TYPE 2
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#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
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#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
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#define LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff)
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/*
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* Check for extended topology enumeration cpuid leaf 0xb and if it
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* exists, use it for populating initial_apicid and cpu topology
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* detection.
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*/
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void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_SMP
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unsigned int eax, ebx, ecx, edx, sub_index;
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unsigned int ht_mask_width, core_plus_mask_width;
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unsigned int core_select_mask, core_level_siblings;
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if (c->cpuid_level < 0xb)
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return;
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cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
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/*
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* check if the cpuid leaf 0xb is actually implemented.
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*/
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if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE))
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return;
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set_cpu_cap(c, X86_FEATURE_XTOPOLOGY);
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/*
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* initial apic id, which also represents 32-bit extended x2apic id.
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*/
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c->initial_apicid = edx;
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/*
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* Populate HT related information from sub-leaf level 0.
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*/
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core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx);
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core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
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sub_index = 1;
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do {
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cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
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/*
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* Check for the Core type in the implemented sub leaves.
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*/
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if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
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core_level_siblings = LEVEL_MAX_SIBLINGS(ebx);
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core_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
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break;
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}
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sub_index++;
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} while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
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core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width;
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#ifdef CONFIG_X86_32
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c->cpu_core_id = phys_pkg_id(c->initial_apicid, ht_mask_width)
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& core_select_mask;
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c->phys_proc_id = phys_pkg_id(c->initial_apicid, core_plus_mask_width);
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/*
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* Reinit the apicid, now that we have extended initial_apicid.
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*/
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c->apicid = phys_pkg_id(c->initial_apicid, 0);
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#else
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c->cpu_core_id = phys_pkg_id(ht_mask_width) & core_select_mask;
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c->phys_proc_id = phys_pkg_id(core_plus_mask_width);
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/*
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* Reinit the apicid, now that we have extended initial_apicid.
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*/
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c->apicid = phys_pkg_id(0);
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#endif
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c->x86_max_cores = (core_level_siblings / smp_num_siblings);
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printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
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c->phys_proc_id);
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if (c->x86_max_cores > 1)
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printk(KERN_INFO "CPU: Processor Core ID: %d\n",
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c->cpu_core_id);
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return;
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#endif
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}
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#ifdef CONFIG_X86_PAT
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void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
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{
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if (!cpu_has_pat)
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pat_disable("PAT not supported by CPU.");
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switch (c->x86_vendor) {
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case X86_VENDOR_INTEL:
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/*
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* There is a known erratum on Pentium III and Core Solo
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* and Core Duo CPUs.
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* " Page with PAT set to WC while associated MTRR is UC
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* may consolidate to UC "
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* Because of this erratum, it is better to stick with
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* setting WC in MTRR rather than using PAT on these CPUs.
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*
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* Enable PAT WC only on P4, Core 2 or later CPUs.
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*/
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if (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 15))
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return;
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pat_disable("PAT WC disabled due to known CPU erratum.");
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return;
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case X86_VENDOR_AMD:
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case X86_VENDOR_CENTAUR:
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case X86_VENDOR_TRANSMETA:
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return;
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}
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pat_disable("PAT disabled. Not yet verified on this CPU type.");
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}
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#endif
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