![Arnd Bergmann](/assets/img/avatar_default.png)
Platform data for device drivers should be defined in include/linux/platform_data/*.h, not in the architecture and platform specific directories. This moves such data out of the imx include directories Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com> Acked-by: Sascha Hauer <kernel@pengutronix.de> Acked-by: Vinod Koul <vinod.koul@linux.intel.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Dan Williams <djbw@fb.com> Cc: "Ben Dooks (embedded platforms)" <ben-linux@fluff.org> Cc: "Wolfram Sang (embedded platforms)" <w.sang@pengutronix.de> Cc: Chris Ball <cjb@laptop.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Alan Cox <alan@linux.intel.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: Liam Girdwood <lrg@ti.com> Cc: Javier Martin <javier.martin@vista-silicon.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
172 lines
5.4 KiB
C
172 lines
5.4 KiB
C
/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <linux/platform_data/usb-ehci-mxc.h>
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#define MXC_OTG_OFFSET 0
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#define MXC_H1_OFFSET 0x200
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#define MXC_H2_OFFSET 0x400
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/* USB_CTRL */
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#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
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#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
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#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
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#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
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#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
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/* USB_PHY_CTRL_FUNC */
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#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */
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#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
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#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */
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#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
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#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */
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/* USBH2CTRL */
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#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
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#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
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#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
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#define MXC_USBCMD_OFFSET 0x140
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/* USBCMD */
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#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
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int mx51_initialize_usb_hw(int port, unsigned int flags)
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{
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unsigned int v;
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void __iomem *usb_base;
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void __iomem *usbotg_base;
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void __iomem *usbother_base;
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int ret = 0;
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usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
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if (!usb_base) {
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printk(KERN_ERR "%s(): ioremap failed\n", __func__);
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return -ENOMEM;
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}
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switch (port) {
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case 0: /* OTG port */
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usbotg_base = usb_base + MXC_OTG_OFFSET;
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break;
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case 1: /* Host 1 port */
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usbotg_base = usb_base + MXC_H1_OFFSET;
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break;
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case 2: /* Host 2 port */
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usbotg_base = usb_base + MXC_H2_OFFSET;
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break;
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default:
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printk(KERN_ERR"%s no such port %d\n", __func__, port);
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ret = -ENOENT;
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goto error;
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}
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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switch (port) {
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case 0: /*OTG port */
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if (flags & MXC_EHCI_INTERNAL_PHY) {
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
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else
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v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
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/* OC/USBPWR is used */
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v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
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} else {
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/* OC/USBPWR is not used */
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v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
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}
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
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else
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v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
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if (flags & MXC_EHCI_WAKEUP_ENABLED)
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v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
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else
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v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_OTG_UCTRL_OPM_BIT;
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else
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v |= MXC_OTG_UCTRL_OPM_BIT;
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__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
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}
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break;
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case 1: /* Host 1 */
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/*Host ULPI */
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v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
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if (flags & MXC_EHCI_WAKEUP_ENABLED) {
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/* HOST1 wakeup/ULPI intr enable */
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v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
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} else {
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/* HOST1 wakeup/ULPI intr disable */
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v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
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}
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
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else
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v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
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__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
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v |= MXC_H1_OC_POL_BIT;
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else
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v &= ~MXC_H1_OC_POL_BIT;
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
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else
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v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
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v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
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if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
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/* Interrupt Threshold Control:Immediate (no threshold) */
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v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
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__raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
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break;
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case 2: /* Host 2 ULPI */
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v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
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if (flags & MXC_EHCI_WAKEUP_ENABLED) {
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/* HOST1 wakeup/ULPI intr enable */
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v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
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} else {
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/* HOST1 wakeup/ULPI intr disable */
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v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
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}
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if (flags & MXC_EHCI_POWER_PINS_ENABLED)
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v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
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else
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v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
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__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
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break;
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}
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error:
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iounmap(usb_base);
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return ret;
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}
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