3ee851e212
This patch add basic rk3288 smp support. Only cortex-A9 need invalid L1, A7/A12/A15/A17 should not invalid L1, since for A7/A12/A15, the invalidation would be taken as clean and invalidate. If you use the software manual invalidation instead of hardware invalidation (assert l1/l2rstdisable during reset) after reset, there is tiny change that some cachelines would be in dirty and valid state after reset(since the ram content would be random value after reset), then the unexpected clean might lead to system crash. It is a known issue for the A12/A17 MPCore multiprocessor that the active processors might be stalled when the individual processor is powered down, we can avoid this prolbem by softreset the processor before power it down. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
34 lines
1 KiB
ArmAsm
34 lines
1 KiB
ArmAsm
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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ENTRY(rockchip_secondary_startup)
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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ldr r1, =0x00000c09 @ Cortex-A9 primary part number
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teq r0, r1
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beq v7_invalidate_l1
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b secondary_startup
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ENDPROC(rockchip_secondary_startup)
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ENTRY(rockchip_secondary_trampoline)
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ldr pc, 1f
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ENDPROC(rockchip_secondary_trampoline)
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.globl rockchip_boot_fn
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rockchip_boot_fn:
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1: .space 4
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ENTRY(rockchip_secondary_trampoline_end)
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