cb1ed9e117
Yeeloong 2F netbook has an KB3310B embedded controller to manage the LID action. When the LID is closed or opened a SCI interrupt is sent out and the corresponding event is saved to an EC register for later query. Allow the LID open interrupt to wake the processor from wait mode if it is in the suspend mode. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/685/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
/*
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* Copyright (C) 2007 Lemote Inc.
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/irq_cpu.h>
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#include <asm/i8259.h>
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#include <asm/mipsregs.h>
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#include <loongson.h>
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#include <machine.h>
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#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
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#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
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#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
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#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
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#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
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#define LOONGSON_INT_BIT_INT0 (1 << 11)
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#define LOONGSON_INT_BIT_INT1 (1 << 12)
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/*
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* The generic i8259_irq() make the kernel hang on booting. Since we cannot
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* get the irq via the IRR directly, we access the ISR instead.
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*/
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int mach_i8259_irq(void)
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{
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int irq, isr;
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irq = -1;
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if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
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spin_lock(&i8259A_lock);
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isr = inb(PIC_MASTER_CMD) &
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~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
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if (!isr)
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isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
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irq = ffs(isr) - 1;
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if (unlikely(irq == 7)) {
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/*
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* This may be a spurious interrupt.
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*
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* Read the interrupt status register (ISR). If the most
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* significant bit is not set then there is no valid
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* interrupt.
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*/
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outb(0x0B, PIC_MASTER_ISR); /* ISR register */
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if (~inb(PIC_MASTER_ISR) & 0x80)
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irq = -1;
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}
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spin_unlock(&i8259A_lock);
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}
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return irq;
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}
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EXPORT_SYMBOL(mach_i8259_irq);
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static void i8259_irqdispatch(void)
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{
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int irq;
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irq = mach_i8259_irq();
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if (irq >= 0)
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do_IRQ(irq);
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else
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spurious_interrupt();
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}
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void mach_irq_dispatch(unsigned int pending)
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{
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if (pending & CAUSEF_IP7)
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do_IRQ(LOONGSON_TIMER_IRQ);
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else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */
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#ifdef CONFIG_OPROFILE
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do_IRQ(LOONGSON2_PERFCNT_IRQ);
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#endif
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bonito_irqdispatch();
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} else if (pending & CAUSEF_IP3) /* CPU UART */
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do_IRQ(LOONGSON_UART_IRQ);
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else if (pending & CAUSEF_IP2) /* South Bridge */
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i8259_irqdispatch();
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else
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spurious_interrupt();
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}
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void __init set_irq_trigger_mode(void)
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{
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/* setup cs5536 as high level trigger */
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LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
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LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
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}
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static irqreturn_t ip6_action(int cpl, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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struct irqaction ip6_irqaction = {
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.handler = ip6_action,
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.name = "cascade",
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.flags = IRQF_SHARED,
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};
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struct irqaction cascade_irqaction = {
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.handler = no_action,
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.name = "cascade",
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};
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void __init mach_init_irq(void)
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{
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/* init all controller
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* 0-15 ------> i8259 interrupt
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* 16-23 ------> mips cpu interrupt
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* 32-63 ------> bonito irq
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*/
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/* Sets the first-level interrupt dispatcher. */
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mips_cpu_irq_init();
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init_i8259_irqs();
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bonito_irq_init();
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/* setup north bridge irq (bonito) */
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setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction);
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/* setup source bridge irq (i8259) */
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setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction);
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}
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